Inventor
Ghasi R. Agrawal
Inventor
San Jose, CA, US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores71%
G06FElectric digital data processing9%
G01RMeasuring electric variables6%
B05BSpraying apparatus3%
F16KValves3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H10BElectronic memory devices3%
H10DInorganic electric semiconductor devices3%
PatentTitleYear
10,911,438Secure detection and management of compromised credentials using a salt and a set model20217,913,125'BISR mode to test the redundant elements and regular functional memory to avoid test escapes'20117,640,152'Accurate pin-based memory power model using arc-based characterization'20097,536,611'Hard BISR scheme allowing field repair and usage of reliability controller'20097,493,541'Method and system for performing built-in-self-test routines using an accumulator to store fault information'20097,376,541'Accurate pin-based memory power model using arc-based characterization'20087,272,814'Reconfiguring a RAM to a ROM using layers of metallization'20077,260,758'Method and system for performing built-in self-test routines using an accumulator to store fault information'20077,260,700'Method and apparatus for separating native, functional and test configurations of memory'20077,185,243'Testing implementation suitable for built-in self-repair (BISR) memories'20077,180,819'Converting dual port memory into 2 single port memories'20077,076,699'Method for testing semiconductor devices having built-in self repair (BISR) memory'20066,928,591'Fault repair controller for redundant memory integrated circuits'20056,928,598'Scan method for built-in-self-repair (BISR)'20056,898,143'Sharing fuse blocks between memories in hard-BISR'20056,870,782'Row redundancy memory repair scheme with shift to eliminate timing penalty'20056,871,297'Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories'20056,643,204'Self-time scheme to reduce cycle time for memories'20036,640,321'Built-in self-repair of semiconductor memory with redundant row testing using background pattern'20036,507,524'Integrated circuit memory having column redundancy'20036,483,754'Self-time scheme to reduce cycle time for memories'20026,438,046'System and method for providing row redundancy with no timing penalty for built-in-self-repair (BISR) in high density memories'20026,404,700'Low power high density asynchronous memory architecture'20026,370,078'Way to compensate the effect of coupling between bitlines in a multi-port memories'20026,366,508'Integrated circuit memory having column redundancy with no timing penalty'20026,341,092'Designing memory for testability to support scan capability in an asic design'20026,288,598'Laser fuse circuit design'20016,233,197'Multi-port semiconductor memory and compiler having capacitance compensation'20016,185,140'Sensing architecture with decreased precharge voltage levels'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2008Patents assigned to LSI LOGIC CORP (21)· patent assignee history
2001–2009Based in San Jose, CA, US· patent location history
2005–2011Based in Sunnyvale, CA, US· patent location history
2007–2011Patents assigned to LSI CORP (6)· patent assignee history
2007Based in Cupertino, CA, US· patent location history
2009Patents assigned to LST CORP (1)· patent assignee history
2021Patents assigned to SHAPE SECURITY INC (1)· patent assignee history
2021Based in Mountain View, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 21 | 2001–2008 |
| LSI CORP | 6 | 2007–2011 |
| LST CORP | 1 | 2009 |
| SHAPE SECURITY INC | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 18 | 2001–2009 |
| Sunnyvale, California, US | 9 | 2005–2011 |
| Mountain View, California, US | 1 | 2021 |
| Cupertino, California, US | 1 | 2007 |