Inventor

Darren L. Abramson

Inventor

Folsom, CA, US

Overview

1998–2019

Patent span

Physics

Primary field (CPC G)

Patents· 34 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing77%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%

H04LTransmission of digital information, e.g. telegraphic communication7%

G09GArrangements or circuits for control of indicating devices using static means to present variable information2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

PatentTitleYear

10,366,017Methods and apparatus to offload media streams in host devices2019 9,990,327Providing multiple roots in a semiconductor device2018 9,424,211'Providing multiple virtual device controllers by redirecting an interrupt from a physical device controller'2016 8,930,602'Providing adaptive bandwidth allocation for a fixed priority arbiter'2015 8,386,682'Method, apparatus and system for maintaining transaction coherecy in a multiple data bus platform'2013 8,347,015'Power-optimized frame synchronization for multiple USB controllers with non-uniform frame rates'2013 8,069,294'Power-optimized frame synchronization for multiple USB controllers with non-uniform frame rates'2011 7,990,999'Starvation prevention scheme for a fixed priority PCE-express arbiter with grant counters using arbitration pools'2011 7,913,100'Opportunistic initiation of data traffic'2011 7,620,833'Power saving for isochronous data streams in a computer system'2009 7,525,986'Starvation prevention scheme for a fixed priority PCI-Express arbiter with grant counters using arbitration pools'2009 7,502,377'PCI to PCI express protocol conversion'2009 7,340,550'USB schedule prefetcher for low power'2008 7,228,366'Method and apparatus for deterministic removal and reclamation of work items from an expansion bus schedule'2007 7,093,115'Method and apparatus for detecting an interruption in memory initialization'2006 6,665,756'Bus interface unit for reflecting state information for a transfer request to a requesting device'2003 6,643,716'Method and apparatus for processing serial data using a single receive fifo'2003 6,594,717'Apparatus and method for dedicated interconnection over a shared external bus'2003 6,529,980'Superposition of host bridge status onto an existing request/grant signaling protocol'2003 6,502,146'Apparatus and method for dedicated interconnection over a shared external bus'2002 6,499,077'Bus interface unit for reflecting state information for a transfer request to a requesting device'2002 6,473,843'Alternate access mechanism for saving and restoring state of write-only register'2002 6,385,671'Method/apparatus for flushing DMA transmit packet in FIFO when self-ID code generated by counter after bus reset is different than FIFO message self-ID field'2002 6,374,321'Mechanisms for converting address and data signals to interrupt message signals'2002 6,212,609'Alternate access mechanism for saving and restoring state of read-only register'2001 6,192,428'Method/apparatus for dynamically changing FIFO draining priority through asynchronous or isochronous DMA engines in response to packet type and predetermined high watermark being reached'2001 6,134,625'Method and apparatus for providing arbitration between multiple data streams'2000 6,131,135'Arbitration method for a system with two USB host controllers'2000 6,000,043'Method and apparatus for management of peripheral devices coupled to a bus'1999 5,991,304'Method and apparatus for minimizing asynchronous transmit FIFO under-run and receive FIFO over-run conditions'1999 5,951,667'Method and apparatus for connecting expansion buses to a peripheral component interconnect bus'1999 5,889,968'Method and apparatus for interlocking a broadcast message on a bus'1999 5,857,117'Apparatus and method for multiplexing integrated device electronics circuitry with an industry standard architecture bus'1999 5,768,545'Collect all transfers buffering mechanism utilizing passive release for a multiple bus environment'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2019Patents assigned to INTEL CORP (34)· patent assignee history

1998–2019Based in Folsom, CA, US· patent location history

2011–2015Patents assigned to ABRAMSON DARREN L (4)· patent assignee history

2011–2013Patents assigned to DERR MICHAEL N (2)· patent assignee history

2011–2013Patents assigned to DOUCETTE BRYAN C (2)· patent assignee history

2013–2015Patents assigned to LEE KHEE WOOI (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	34	1998–2019
ABRAMSON DARREN Lself	4	2011–2015
DERR MICHAEL N	2	2011–2013
DOUCETTE BRYAN C	2	2011–2013
LEE KHEE WOOI	2	2013–2015

Locations

Location	Patents	Span
Folsom, California, US	34	1998–2019