Inventor
Darsen D. Lu
Inventor
Mount Kisco, NY, US
Overview
Patents· 37 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices30%
H10DInorganic electric semiconductor devices30%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
H10BElectronic memory devices2%
H10NElectric solid-state devices not otherwise provided for2%
G11CStatic stores1%
PatentTitleYear
10,903,208Distributed decoupling capacitor202110,892,364Dielectric isolated fin with improved fin profile202110,886,385Semiconductor structures having increased channel strain using fin release in gate regions202110,734,477FinFET with reduced parasitic capacitance202010,622,451Flash memory with multiple control gates and flash memory array device made thereof202010,593,663Distributed decoupling capacitor202010,546,955Dielectric isolated fin with improved fin profile202010,347,752Semiconductor structures having increased channel strain using fin release in gate regions201910,262,991Distributed decoupling capacitor201910,243,042FinFET with reduced parasitic capacitance201910,177,223FinFET with reduced parasitic capacitance201910,153,157P-FET with graded silicon-germanium channel201810,056,474Semiconductor structures having increased channel strain using fin release in gate regions20189,997,540Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices20189,966,387Strain release in pFET regions20189,954,083Semiconductor structures having increased channel strain using fin release in gate regions20189,917,188'Dielectric isolated fin with improved fin profile'20189,825,094'FinFET PCM access transistor having gate-wrapped source and drain regions'20179,825,093'FinFET PCM access transistor having gate-wrapped source and drain regions'20179,786,737'FinFET with reduced parasitic capacitance'20179,761,610'Strain release in PFET regions'20179,653,541'Structure and method to make strained FinFET with improved junction capacitance and low leakage'20179,583,492'Structure and method for advanced bulk fin isolation'20179,583,624'Asymmetric finFET memory access transistor'20179,564,439'Structure and method for advanced bulk fin isolation'20179,553,173'Asymmetric finFET memory access transistor'20179,548,386'Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices'20179,548,213'Dielectric isolated fin with improved fin profile'20179,543,323'Strain release in PFET regions'20179,525,027'Lateral bipolar junction transistor having graded SiGe base'20169,515,171'Radiation tolerant device structure'20169,455,250'Distributed decoupling capacitor'20169,362,400'Semiconductor device including dielectrically isolated finFETs and buried stressor'20169,299,618'Structure and method for advanced bulk fin isolation'20169,276,113'Structure and method to make strained FinFET with improved junction capacitance and low leakage'20169,209,065'Engineered substrate and device for co-integration of strained silicon and relaxed silicon'20159,034,715'Method and structure for dielectric isolation in a fin field effect transistor'2015Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2015–2021Patents assigned to IBM (33)· patent assignee history
2015–2021Based in Mount Kisco, NY, US· patent location history
2015Based in Yorktown Heights, NY, US· patent location history
2016–2017Patents assigned to GLOBALFOUNDRIES INC (3)· patent assignee history
2018–2021Based in Westchester, NY, US· patent location history
2018–2021Based in Taichung, TW· patent location history
2020Patents assigned to UNIV NAT CHENG KUNG (1)· patent assignee history
2020Based in Tainan, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 33 | 2015–2021 |
| GLOBALFOUNDRIES INC | 3 | 2016–2017 |
| UNIV NAT CHENG KUNG | 1 | 2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Mount Kisco, New York, US | 29 | 2015–2021 |
| Westchester, New York, US | 4 | 2018–2021 |
| Taichung, TW | 2 | 2018–2021 |
| Tainan, TW | 1 | 2020 |
| Yorktown Heights, New York, US | 1 | 2015 |