LexDanaLexDanabeta
Inventor

Henry Chien

Inventor
San Jose, CA, US

Overview

84→
Patents
1993–2018
Patent span
Electricity
Primary field (CPC H)

Patents· 84 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices32%
H10DInorganic electric semiconductor devices20%
H01LSemiconductor devices16%
G11CStatic stores8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
H10NElectric solid-state devices not otherwise provided for4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
B82YSpecific uses or applications of nanostructures2%
C07FAcyclic, carbocyclic or heterocyclic compounds containing elements other than carbon, hydrogen, halogen, oxygen, nitrogen, sulfur, selenium or tellurium2%
PatentTitleYear
9,870,945'Crystalline layer stack for forming conductive layers in a three-dimensional memory structure'20189,853,043Method of making a multilevel memory stack structure using a cavity containing a sacrificial fill material20179,728,546'3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same'20179,728,551'Multi-tier replacement memory stack structure integration scheme'20179,716,101'Forming 3D memory cells after word line replacement'20179,698,149'Non-volatile memory with flat cell structures and air gap isolation'20179,672,917'Stacked vertical memory array architectures, systems and methods'20179,666,590'High stack 3D memory and method of making'20179,659,956'Three-dimensional memory device containing source select gate electrodes with enhanced electrical isolation'20179,620,514'3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same'20179,583,500'Multilevel memory stack structure and methods of manufacturing the same'20179,530,790'Three-dimensional memory device containing CMOS devices over memory stack structures'20169,530,785'Three-dimensional memory devices having a single layer channel and methods of making thereof'20169,524,976'Method of integrating select gate source and memory hole for three-dimensional non-volatile memory device'20169,524,779'Three dimensional vertical NAND device with floating gates'20169,520,406'Method of making a vertical NAND device using sequential etching of multilayer stacks'20169,515,080'Vertical NAND and method of making thereof using sequential stack etching and landing pad'20169,502,471'Multi tier three-dimensional memory devices including vertically shared bit lines'20169,466,644'Resistance-switching memory cell with multiple raised structures in a bottom electrode'20169,449,982'Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks'20169,449,981'Three dimensional NAND string memory devices and methods of fabrication thereof'20169,437,813'Method for forming resistance-switching memory cell with multiple electrodes using nano-particle hard mask'20169,379,120'Metal control gate structures and air gap isolation in non-volatile memory'20169,356,031'Three dimensional NAND string memory devices with voids enclosed between control gate electrodes'20169,331,181'Nanodot enhanced hybrid floating gate for non-volatile memory devices'20169,252,151'Three dimensional NAND device with birds beak containing floating gates and method of making thereof'20169,230,987'Multilevel memory stack structure and methods of manufacturing the same'20169,227,456'Memories with cylindrical read/write stacks'20169,230,974'Methods of selective removal of blocking dielectric in NAND memory strings'20169,165,940'Three dimensional NAND device with silicide containing floating gates and method of making thereof'20159,123,890'Resistance-switching memory cell with multiple raised structures in a bottom electrode'20159,099,496'Method of forming an active area with floating gate negative offset profile in FG NAND memory'20159,093,480'Spacer passivation for high aspect ratio etching of multilayer stacks for three dimensional NAND device'20158,987,087'Three dimensional NAND device with birds beak containing floating gates and method of making thereof'20158,946,023'Method of making a vertical NAND device using sequential etching of multilayer stacks'20158,946,022'Integrated nanostructure-based non-volatile memory fabrication'20158,946,048'Method of fabricating non-volatile memory with flat cell structures and air gap isolation'20158,946,803'Method of forming a floating gate with a wide base and a narrow stem'20158,928,061'Three dimensional NAND device with silicide containing floating gates'20158,895,437'Method for forming staircase word lines in a 3D non-volatile memory having vertical bit lines'20148,884,357'Vertical NAND and method of making thereof using sequential stack etching and landing pad'20148,803,220'P-type control gate in non-volatile storage'20148,710,481'Non-volatile memory cell containing a nano-rail electrode'20148,693,233'Re-writable resistance-switching memory with balanced series stack'20148,546,214'P-type control gate in non-volatile storage and methods for forming same'20138,492,224'Metal control gate structures and air gap isolation in non-volatile memory'20138,461,641'Ultrahigh density vertical NAND memory device and method of making thereof'20138,383,479'Integrated nanostructure-based non-volatile memory fabrication'20138,330,208'Ultrahigh density monolithic three dimensional vertical NAND string memory device and method of making thereof'20128,288,225'Method of reducing coupling between floating gates in nonvolatile memory'20128,207,036'Method for forming self-aligned dielectric cap above floating gate'2012RE043417'Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND'20128,187,936'Ultrahigh density vertical NAND memory device and method of making thereof'20128,105,867'Self-aligned three-dimensional non-volatile memory fabrication'20128,030,160'Methods of forming NAND flash memory with fixed charge'20117,915,664'Non-volatile memory with sidewall channels and raised source/drain regions'20117,910,434'Method of reducing coupling between floating gates in nonvolatile memory'20117,795,080'Methods of forming integrated circuit devices using composite spacer structures'20107,745,660'Process for recovering a crystalline product from solution'20107,732,275'Methods of forming NAND flash memory with fixed charge'20107,619,926'NAND flash memory with fixed charge'20097,615,445'Methods of reducing coupling between floating gates in nonvolatile memory'20097,504,686'Self-aligned non-volatile memory cell'20097,504,534'Reaction systems for making N-(phosphonomethyl) glycine compounds'20097,495,282'NAND memory with virtual channel'20097,494,870'Methods of forming NAND memory with virtual channel'20097,491,999'Non-volatile memory cells utilizing substrate trenches'20097,221,008'Bitline direction shielding to avoid cross coupling between adjacent cells for NAND flash memory'20077,179,936'Process for recovering a crystalline product from solution'20077,170,786'Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND'20077,105,406'Self aligned non-volatile memory cell and process for fabrication'20067,087,951'Non-volatile memory cells utilizing substrate trenches'20067,015,351'Reaction systems for making N-(phosphonomethyl) glycine compounds'20066,936,887'Non-volatile memory cells utilizing substrate trenches'20056,898,121'Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND'20056,894,930'Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND'20055,756,385'Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers'19985,747,359'Method of patterning polysilicon layers on substrate'19985,654,217'Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers'19975,534,456'Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with sidewall spacers'19965,328,616'Methods and apparatus for treating electroless plating baths'19945,306,336'Sulfate-free electroless copper plating baths'19945,277,817'Apparatus and methods for treating electroless plating baths'19945,258,061'Electroless nickel plating baths'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2010Based in St. Louis, MO, US· patent location history
1996–2011Patents assigned to SANDISK CORP (21)· patent assignee history
1996–2018Based in San Jose, CA, US· patent location history
2005–2007Based in Manassas, VA, US· patent location history
2011–2018Patents assigned to SANDISK TECHNOLOGIES INC (45)· patent assignee history
2012–2015Patents assigned to CHIEN HENRY (13)· patent assignee history
2012–2015Patents assigned to MATAMIS GEORGE (10)· patent assignee history
2016–2018Patents assigned to SANDISK TECHNOLOGIES LLC (22)· patent assignee history
2017Based in Milpitas, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SANDISK TECHNOLOGIES INC452011–2018
SANDISK TECHNOLOGIES LLC222016–2018
SANDISK CORP211996–2011
CHIEN HENRYself132012–2015
MATAMIS GEORGE102012–2015
Locations
LocationPatentsSpan
San Jose, California, US691996–2018
St. Louis, MO, US81993–2010
Manassas, Virginia, US52005–2007
Milpitas, California, US22017