Inventor
Patrik D'Haeseleer
Inventor
Atherton, CA, US
Overview
Patents· 4 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing38%
A61KPreparations for medical, dental or toiletry purposes13%
C07KPeptides13%
C12NMicroorganisms or enzymes13%
C12QMeasuring or testing processes involving enzymes, nucleic acids or microorganisms13%
Y02ATechnologies for adaptation to climate change13%
PatentTitleYear
10,808,232Dynamically-adaptive live therapeutic agents and methods of use thereof20205,859,781'Method and apparatus for computing minimum wirelength position (MWP) for cell in cell placement for integrated circuit chip'19995,638,293'Optimal pad location method for microelectronic circuit cell placement'19975,619,419'Method of cell placement for an itegrated circuit chip comprising integrated placement and cell overlap removal'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–1999Patents assigned to LSI LOGIC CORP (3)· patent assignee history
1997–1999Based in Atherton, CA, US· patent location history
2020Patents assigned to L LIVERMORE NAT SECURITY LLC (1)· patent assignee history
2020Based in Alameda, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 3 | 1997–1999 |
| L LIVERMORE NAT SECURITY LLC | 1 | 2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Atherton, California, US | 3 | 1997–1999 |
| Alameda, California, US | 1 | 2020 |