Inventor
Manish Pandey
Inventor
San Jose, CA, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing83%
G06NComputing arrangements based on specific computational models8%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes4%
H04NPictorial communication, e.g. television4%
PatentTitleYear
11,074,302Anomaly visualization for computerized models202110,521,536RTL verification using computational complexity-based property ranking and scheduling201910,503,853Formal verification using cached search path information to verify previously proved/disproved properties201910,140,403Managing model checks of sequential designs20189,430,595'Managing model checks of sequential designs'20168,627,249'Method and system for generating design constraints'2014RE044479'Method and mechanism for implementing electronic designs having power information specifications background'20138,516,422'Method and mechanism for implementing electronic designs having power information specifications background'20138,442,111'Optimal power usage in encoding data streams'20138,209,648'Verifying multiple constraints for circuit designs'20127,962,886'Method and system for generating design constraints'20117,739,629'Method and mechanism for implementing electronic designs having power information specifications background'20107,694,251'Method and system for verifying power specifications of a low power design'20107,669,165'Method and system for equivalence checking of a low power design'20107,644,380'Method for analyzing circuits having MOS devices'20107,620,918'Method and system for logic equivalence checking'20097,620,919'Method and system for logic equivalence checking'20097,587,690'Method and system for global coverage analysis'20097,266,790'Method and system for logic equivalence checking'20076,848,084'Method and apparatus for verification of memories at multiple abstraction levels'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2014Patents assigned to CADENCE DESIGN SYSTEMS INC (14)· patent assignee history
2005–2014Based in San Jose, CA, US· patent location history
2010–2019Based in Saratoga, CA, US· patent location history
2012–2014Patents assigned to PANDEY MANISH (4)· patent assignee history
2013Patents assigned to BHATIA SANDEEP (2)· patent assignee history
2013Patents assigned to CHEN PINHONG (2)· patent assignee history
2013Based in Thane, IN· patent location history
2016–2019Patents assigned to SYNOPSYS INC (4)· patent assignee history
2021Based in Bangalore, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CADENCE DESIGN SYSTEMS INC | 14 | 2005–2014 |
| PANDEY MANISHself | 4 | 2012–2014 |
| SYNOPSYS INC | 4 | 2016–2019 |
| BHATIA SANDEEP | 2 | 2013 |
| CHEN PINHONG | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 12 | 2005–2014 |
| Saratoga, California, US | 6 | 2010–2019 |
| Bangalore, IN | 1 | 2021 |
| Thane, IN | 1 | 2013 |