Inventor
Kiminori Ishido
Inventor
Tokyo, JP
Overview
Patents· 15 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H05Kprimary
H05KPrinted circuits22%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1022%
H01LSemiconductor devices16%
C23CCoating metallic material8%
C23FNon-mechanical removal of metallic material from surface5%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
Y10TTechnical subjects covered by former us classification5%
B23KSoldering or unsoldering3%
G02BOptical elements, systems or apparatus3%
PatentTitleYear
10,256,196Semiconductor device and method for manufacturing same20199,685,376'Semiconductor device and method of manufacturing semiconductor device'20179,635,762'Semiconductor package'20179,553,052'Magnetic shielding package of non-volatile magnetic memory element'20179,368,474'Manufacturing method for semiconductor device'20169,362,200'Heat sink in the aperture of substrate'20168,367,939'Interconnect substrate, method of manufacturing interconnect substrate and semiconductor device'20138,174,117'Semiconductor device and method of manufacturing the same'20126,791,675'Optical waveguide path, manufacturing method and coupling method of the same, and optical waveguide path coupling structure'20045,746,813'Surface protection material for printed circuit board and process of forming surface protection films'19985,658,611'Surface protection material for printed circuit board and process of forming surface protection films'19975,464,725'Method of manufacturing a printed wiring board'19955,458,907'Method of manufacturing printed circuit boards having an oxidation proof coating on a copper or copper alloy circuit pattern'19955,324,535'Process of coating printed wiring board with solid solder resist pattern formed from liquid and dry solder resist films'19945,258,094'Method for producing multilayer printed wiring boards'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–1998Patents assigned to NEC CORP (6)· patent assignee history
1993–2004Based in Tokyo, JP· patent location history
2012–2013Patents assigned to ISHIDO KIMINORI (2)· patent assignee history
2012–2013Patents assigned to RENESAS ELECTRONICS CORP (2)· patent assignee history
2012–2017Based in Kanagawa, JP· patent location history
2016–2019Patents assigned to J DEVICES CORP (3)· patent assignee history
2017Patents assigned to J-DEVICES CORP (3)· patent assignee history
2017–2019Based in Yokohama, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC CORP | 6 | 1993–1998 |
| J DEVICES CORP | 3 | 2016–2019 |
| J-DEVICES CORP | 3 | 2017 |
| ISHIDO KIMINORIself | 2 | 2012–2013 |
| RENESAS ELECTRONICS CORP | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 7 | 1993–2004 |
| Kanagawa, JP | 5 | 2012–2017 |
| Yokohama, JP | 3 | 2017–2019 |