Inventor
Jose A. Tierno
Inventor
Stamford, CT, US
Overview
Patents· 52 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Lprimary
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses28%
G06NComputing arrangements based on specific computational models17%
G06FElectric digital data processing10%
H03KPulse technique10%
G11CStatic stores7%
H03MCoding6%
H04LTransmission of digital information, e.g. telegraphic communication6%
G01RMeasuring electric variables3%
G05FSystems for regulating electric or magnetic variables3%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner3%
PatentTitleYear
11,023,403Chip to chip interface with scalable bandwidth202110,810,487Reconfigurable and customizable general-purpose circuits for neural networks202010,628,732Reconfigurable and customizable general-purpose circuits for neural networks202010,521,391Chip to chip interface with scalable bandwidth201910,331,998Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network20199,953,261Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices20189,946,969Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices20189,818,058'Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation'20179,800,251'Loop parameter sensor using repetitive phase errors'20179,460,383'Reconfigurable and customizable general-purpose circuits for neural networks'20169,373,073'Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation'20169,269,042'Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices'20169,239,984'Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network'20169,240,789'Sub-rate low-swing data receiver'20169,207,695'Calibration schemes for charge-recycling stacked voltage domains'20159,157,950'Loop parameter sensor using repetitive phase errors'20158,994,457'Transimpedance amplifier'20158,949,685'Soft error protection in individual memory devices'20158,898,097'Reconfigurable and customizable general-purpose circuits for neural networks'20148,856,055'Reconfigurable and customizable general-purpose circuits for neural networks'20148,797,084'Calibration schemes for charge-recycling stacked voltage domains'20148,773,215'Fully decoupled LC-tank based oscillator topology for low phase noise and high oscillation amplitude applications'20148,704,566'Hybrid phase-locked loop architectures'20148,704,567'Hybrid phase-locked loop architectures'20148,675,722'Methods and apparatus for snapshot-based equalization of a communications channel'20148,665,034'Varactor tuning control using redundant numbering'20148,640,070'Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)'20148,629,701'PLL bandwidth correction with offset compensation'20148,593,226'Transimpedance amplifier'20138,570,079'Reducing phase locked loop phase lock time'20138,493,113'PLL bandwidth correction with offset compensation'20138,476,945'Phase profile generator'20138,375,269'Data transmission system and method of correcting an error in parallel data paths of a data transmission system'20138,264,285'Method and apparatus for low latency proportional path in a digitally controlled system'20128,222,936'Phase and frequency detector with output proportional to frequency difference'20128,138,840'Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control'20127,863,952'Method and circuit for controlling clock frequency of an electronic circuit with noise mitigation'20117,847,641'Digital phase and frequency detector'20107,772,900'Phase-locked loop circuits and methods implementing pulsewidth modulation for fine tuning control of digitally controlled oscillators'20107,750,701'Phase-locked loop circuits and methods implementing multiplexer circuit for fine tuning control of digitally controlled oscillators'20107,721,182'Soft error protection in individual memory devices'20107,602,869'Methods and apparatus for clock synchronization and data recovery in a receiver'20097,579,887'Technique for efficiently managing both short-term and long-term frequency adjustments of an electronic circuit clock signal'20097,509,568'Error type identification circuit for identifying different types of errors in communications devices'20097,498,894'Varactor system having real or apparent low capacitance density'20097,443,251'Digital phase and frequency detector'20087,352,297'Method and apparatus for efficient implementation of digital filter with thermometer-code-like output'20087,107,301'Method and apparatus for reducing latency in a digital signal processing device'20066,859,071'Pseudofooter circuit for dynamic CMOS (Complementary metal-oxide-semiconductor) logic'20056,795,842'Method and apparatus for comparing two binary numbers with a power-of-two threshold'20046,650,699'Methods and apparatus for timing recovery from a sampled and equalized data signal'20035,451,890'Gallium arsenide source follower FET logic family with diodes for preventing leakage currents'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995Based in Pasadena, CA, US· patent location history
2003–2020Patents assigned to IBM (48)· patent assignee history
2003–2019Based in Stamford, CT, US· patent location history
2005Based in Austin, TX, US· patent location history
2012–2016Patents assigned to TIERNO JOSE A (20)· patent assignee history
2012–2015Patents assigned to RYLYAKOV ALEXANDER V (11)· patent assignee history
2012–2016Patents assigned to FRIEDMAN DANIEL J (10)· patent assignee history
2012–2014Patents assigned to AINSPAN HERSCHEL A (4)· patent assignee history
2014–2021Based in Palo Alto, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 48 | 2003–2020 |
| TIERNO JOSE Aself | 20 | 2012–2016 |
| RYLYAKOV ALEXANDER V | 11 | 2012–2015 |
| FRIEDMAN DANIEL J | 10 | 2012–2016 |
| AINSPAN HERSCHEL A | 4 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Stamford, CT, US | 44 | 2003–2019 |
| Palo Alto, California, US | 6 | 2014–2021 |
| Austin, Texas, US | 1 | 2005 |
| Pasadena, California, US | 1 | 1995 |