Inventor

Sheldon Aronowitz

Inventor

San Jose, CA, US

Overview

1987–2010

Patent span

Electricity

Primary field (CPC H)

Patents· 77 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1033%

H10DInorganic electric semiconductor devices25%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests14%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%

C23CCoating metallic material6%

Y10TTechnical subjects covered by former us classification2%

B24BMachines, devices, or processes for grinding or polishing2%

C01BNon-metallic elements1%

Y02PClimate change mitigation technologies in the production or processing of goods1%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%

PatentTitleYear

7,829,455'Method for creating barriers for copper diffusion'2010 7,670,645'Method of treating metal and metal salts to enable thin layer deposition in semiconductor processing'2010 7,323,228'Method of vaporizing and ionizing metals for use in semiconductor processing'2008 7,132,336'Method and apparatus for forming a memory structure having an electron affinity region'2006 7,115,991'Method for creating barriers for copper diffusion'2006 7,084,408'Vaporization and ionization of metals for use in semiconductor processing'2006 7,081,296'Method for growing thin films'2006 7,015,168'Low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation'2006 6,989,565'Memory device having an electron trapping layer in a high-K dielectric gate stack'2006 6,930,362'Calcium doped polysilicon gate electrodes'2005 6,919,263'High-K dielectric gate material uniquely formed'2005 6,897,102'Process to minimize polysilicon gate depletion and dopant penetration and to increase conductivity'2005 6,858,195'Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material'2005 6,831,348'Integrated circuit isolation system'2004 6,822,308'Method of chemically altering a silicon surface and associated electrical devices'2004 6,759,337'Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate'2004 6,747,358'Self-aligned alloy capping layers for copper interconnect structures'2004 6,743,474'Method for growing thin films'2004 6,673,498'Method for reticle formation utilizing metal vaporization'2004 6,649,219'Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation'2003 6,627,556'Method of chemically altering a silicon surface and associated electrical devices'2003 6,613,651'Integrated circuit isolation system'2003 6,572,925'Process for forming a low dielectric constant fluorine and carbon containing silicon oxide dielectric material'2003 6,566,262'Method for creating self-aligned alloy capping layers for copper interconnect structures'2003 6,511,925'Process for forming high dielectric constant gate dielectric for integrated circuit structure'2003 6,413,881'PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NITRIDATION OF UPPER SURFACE OF GATE OF OXIDE TO FORM BARRIER OF NITROGEN ATOMS IN UPPER SURFACE REGION OF GATE OXIDE, AND RESULTING PRODUCT'2002 6,331,468'Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers'2001 6,303,047'Low dielectric constant multiple carbon-containing silicon oxide dielectric material for use in integrated circuit structures, and method of making same'2001 6,246,093'Hybrid surface/buried-channel MOSFET'2001 6,180,470'FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements'2001 6,156,620'Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same'2000 6,117,749'Modification of interfacial fields between dielectrics and semiconductors'2000 6,093,936'Integrated circuit with isolation of field oxidation by noble gas implantation'2000 6,090,651'Depletion free polysilicon gate electrodes'2000 6,087,229'Composite semiconductor gate dielectrics'2000 6,060,375'Process for forming re-entrant geometry for gate electrode of integrated circuit structure'2000 6,033,998'Method of forming variable thickness gate dielectrics'2000 5,963,801'Method of forming retrograde well structures and punch-through barriers using low energy implants'1999 5,936,285'Gate array layout to accommodate multi-angle ion implantation'1999 5,904,551'Process for low energy implantation of semiconductor substrate using channeling to form retrograde wells'1999 5,897,381'Method of forming a layer and semiconductor substrate'1999 5,893,952'Apparatus for rapid thermal processing of a wafer'1999 5,877,530'Formation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantation'1999 5,858,864'Process for making group IV semiconductor substrate treated with one or more group IV elements to form barrier region capable of inhibiting migration of dopant materials in substrate'1999 5,837,598'Diffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making same'1998 5,756,369'Rapid thermal processing using a narrowband infrared source and feedback'1998 5,739,580'Oxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidation'1998 5,723,896'Integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate'1998 5,717,238'Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device'1998 5,707,888'Oxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidation'1998 5,654,210'Process for making group IV semiconductor substrate treated with one or more group IV elements to form one or more barrier regions capable of inhibiting migration of dopant materials in substrate'1997 5,585,286'Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device'1996 5,571,744'Defect free CMOS process'1996 5,538,907'Method for forming a CMOS integrated circuit with electrostatic discharge protection'1996 5,508,211'Method of making integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate'1996 5,504,016'Method of manufacturing semiconductor device structures utilizing predictive dopant-dopant interactions'1996 5,468,974'Control and modification of dopant distribution and activation in polysilicon'1995 5,459,085'Gate array layout to accommodate multi angle ion implantation'1995 5,453,389'Defect-free bipolar process'1995 5,441,900'CMOS latchup suppression by localized minority carrier lifetime reduction'1995 5,384,477'CMOS latchup suppression by localized minority carrier lifetime reduction'1995 5,376,560'Method for forming isolated semiconductor structures'1994 5,372,952'Method for forming isolated semiconductor structures'1994 5,357,135'Dmost junction breakdown enhancement'1994 5,312,766'Method of providing lower contact resistance in MOS transistors'1994 5,298,435'Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon'1994 5,296,387'Method of providing lower contact resistance in MOS transistor structures'1994 5,296,386'Method of providing lower contact resistance in MOS transistor structures'1994 5,292,402'Masking material for applications in plasma etching'1994 5,280,185'Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon'1994 5,192,712'Control and moderation of aluminum in silicon using germanium and germanium with boron'1993 5,137,838'Method of fabricating P-buried layers for PNP devices'1992 5,095,358'Application of electronic properties of germanium to inhibit N-type or P-type diffusion in silicon'1992 5,043,292'Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures'1991 4,985,717'MOS memory cell with exponentially-profiled doping and offset floating gate tunnel oxidation'1991 4,746,964'Modification of properties of p-type dopants with other p-type dopants'1988 4,689,667'Method of controlling dopant diffusion and dopant electrical activation by implanted inert gas atoms'1987

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1987–1988Patents assigned to FAIRCHILD SEMICONDUCTOR (2)· patent assignee history

1987–2010Based in San Jose, CA, US· patent location history

1991–2000Patents assigned to NAT SEMICONDUCTOR CORP (19)· patent assignee history

1995–2008Patents assigned to LSI LOGIC CORP (53)· patent assignee history

1995Patents assigned to NAT SEMICONDUCTOR INC (1)· patent assignee history

2010Patents assigned to LSI CORP (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
LSI LOGIC CORP	53	1995–2008
NAT SEMICONDUCTOR CORP	19	1991–2000
FAIRCHILD SEMICONDUCTOR	2	1987–1988
LSI CORP	2	2010
NAT SEMICONDUCTOR INC	1	1995

Locations

Location	Patents	Span
San Jose, California, US	77	1987–2010