Inventor
Dharmesh Kishor Tirthdasani
Inventor
Bangalore, IN
Overview
Patents· 4 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing44%
G11CStatic stores22%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use22%
H03MCoding11%
PatentTitleYear
8,947,966'Power gated memory device with power state indication'20158,923,087'Method and apparatus for decreasing leakage power consumption in power gated memories'20148,707,133'Method and apparatus to reduce a quantity of error detection/correction bits in memory coupled to a data-protected processor port'20148,667,196'Interconnect congestion reduction for memory-mapped peripherals'2014Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2014–2015Patents assigned to LSI CORP (4)· patent assignee history
2014Patents assigned to TIRTHDASANI DHARMESH KISHOR (3)· patent assignee history
2014Patents assigned to KOTHAMASU SRINIVASA RAO (2)· patent assignee history
2014Patents assigned to MEHTA ROMESHKUMAR BHARATKUMAR (2)· patent assignee history
2014–2015Patents assigned to PALANIAPPAN SATHAPPAN (2)· patent assignee history
2014Based in Bangalore, IN· patent location history
2015Based in Ahmedabad, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI CORP | 4 | 2014–2015 |
| TIRTHDASANI DHARMESH KISHORself | 3 | 2014 |
| KOTHAMASU SRINIVASA RAO | 2 | 2014 |
| MEHTA ROMESHKUMAR BHARATKUMAR | 2 | 2014 |
| PALANIAPPAN SATHAPPAN | 2 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bangalore, IN | 3 | 2014 |
| Ahmedabad, IN | 1 | 2015 |