Inventor
Arnold Ginetti
Inventor
Antibes, FR
Overview
Patents· 84 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing88%
H05KPrinted circuits5%
G06TImage data processing or generation, in general2%
G09GArrangements or circuits for control of indicating devices using static means to present variable information1%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%
Y02PClimate change mitigation technologies in the production or processing of goods1%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
11,023,645Method, system, and product to efficiently route interconnections following a free form contour202110,997,333Methods, systems, and computer program product for characterizing an electronic design with a schematic driven extracted view202110,909,302Method, system, and computer program product for characterizing electronic designs with electronic design simplification techniques202110,878,164Methods, systems, and computer program product for interactively probing a multi-fabric electronic design202010,872,192Methods, systems, and computer program product for reducing interferences and disturbances in a multi-fabric electronic design202010,783,312Methods, systems, and computer program product for determining layout equivalence for a multi-fabric electronic design202010,776,555Methods, systems, and computer program product for implementing legal routing tracks across virtual hierarchies and legal placement patterns202010,685,167System, method, and computer program product for displaying bump layout for manufacturing variations202010,678,978Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted view202010,643,016System, method and computer program product for design rule awareness associated with die and package electronic circuit co-design202010,565,342Electronic circuit design editor with overlay of layout and schematic design features202010,558,780Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic design202010,496,772Systems and methods for dynamically generating hierarchical rotating pcells from a static integrated circuit design201910,467,370Methods, systems, and computer program product for implementing a net as a transmission line model in a schematic driven extracted view for an electronic design201910,467,371System, method, and computer program product for floorplanning in an electronic circuit design201910,423,750Technology database independent components for integrated circuit package201910,394,995Methods and systems for schematic driven 2D chaining in an integrated circuit layout201910,354,037Methods, systems, and computer program product for implementing an electronic design by manipulating a hierarchical structure of the electronic design201910,346,573Method and system for performing incremental post layout simulation with layout edits201910,331,841Methods, systems, and computer program product for implementing virtual prototyping for electronic designs201910,289,793System and method to generate schematics from layout-fabrics with a common cross-fabric model201910,285,276Method and apparatus to drive layout of arbitrary EM-coil through parametrized cell201910,282,505Methods, systems, and computer program product for implementing legal routing tracks across virtual hierarchies and legal placement patterns201910,210,299Methods, systems, and computer program product for dynamically abstracting virtual hierarchies for an electronic design201910,192,020Methods, systems, and computer program product for implementing dynamic maneuvers within virtual hierarchies of an electronic design201910,133,841Methods, systems, and computer program product for implementing three-dimensional integrated circuit designs201810,114,733System and method for automated testing of user interface software for visual responsiveness201810,073,942Methods, systems, and computer program product for implementing synchronous clones for an electronic design201810,055,529Methods, systems, and computer program product for implementing a floorplan with virtual hierarchies and figure groups for an electronic design201810,055,528Methods, systems, and computer program product for implementing engineering change orders with figure groups and virtual hierarchies20189,934,354Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design20189,881,119'Methods, systems, and computer program product for constructing a simulation schematic of an electronic design across multiple design fabrics'20189,881,120'Method, system, and computer program product for implementing a multi-fabric mixed-signal design spanning across multiple design fabrics with electrical and thermal analysis awareness'20189,842,183'Methods and systems for enabling concurrent editing of electronic circuit layouts'20179,830,417Methods and systems for generation and editing of parameterized figure group20179,798,840'Methods, systems, and computer program product for implementing a simulation platform with dynamic device model libraries for electronic designs'20179,779,193'Methods, systems, and computer program product for implementing electronic design layouts with symbolic representations'20179,761,204'System and method for accelerated graphic rendering of design layout having variously sized geometric objects'20179,361,415'Method, system, and computer program product for implementing a multi-fabric electronic design spanning across multiple design fabrics'20169,348,960'Method, system, and computer program product for probing or netlisting a multi-fabric electronic design spanning across multiple design fabrics'20169,280,621'Methods, systems, and articles of manufacture for analyzing a multi-fabric electronic design and displaying analysis results for the multi-fabric electronic design spanning and displaying simulation results across multiple design fabrics'20169,223,915'Method, system, and computer program product for checking, verifying, or testing a multi-fabric electronic design spanning across multiple design fabrics'20159,208,137'Method to preview an undo/redo list'20159,141,746'System and method to drag instance master physical shell'20159,129,081'Synchronized three-dimensional display of connected documents'20159,092,586'Version management mechanism for fluid guard ring PCells'20158,910,100'System and method for automatically reconfiguring chain of abutted devices in electronic circuit design'20148,806,405'Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design'20148,762,906'Method, system, and computer program product for implementing multi-power domain digital / mixed signal verification and low power simulation'20148,732,636'Method, system, and computer program product for implementing multi-power domain digital / mixed-signal verification and low power simulation'20148,719,754'System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters'20148,594,988'Method and apparatus for circuit simulation using parallel computing'20138,527,934'Method and system for implementing graphically editable parameterized cells'20138,490,038'System and method for automatic placement of contact cuts and similar structures in integrated circuit layouts'20138,453,136'Change tracking and incremental synchronization of EDA design and technology data'20138,364,656'Method and system for implementing multiuser cached parameterized cells'20138,347,261'Method and system for implementing graphically editable parameterized cells'20138,281,272'System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters'20128,255,845'System and method for generating flat layout'20128,046,730'Systems and methods of editing cells of an electronic circuit design'20117,971,178'System to merge custom and synthesized digital integrated circuit design data'20117,971,175'Method and system for implementing cached parameterized cells'20117,949,987'Method and system for implementing abstract layout structures with parameterized cells'20117,634,743'Method for updating a placed and routed netlist'20097,555,739'Method and apparatus for maintaining synchronization between layout clones'20096,622,291'Method and apparatus for physical budgeting during RTL floorplanning'20036,622,290'Timing verification method employing dynamic abstraction in core/shell partitioning'20036,519,743'Method and system for timing and area driven binary and/or matching'20036,405,345'Updating placement during technology mapping'20026,378,116'Using budgeted required time during technology mapping'20026,170,080'Method and system for floorplanning a circuit design at a high level of abstraction'20016,113,647'Computer aided design system and method using hierarchical and flat netlist circuit representations'20006,086,621'Logic synthesis constraints allocation automating the concurrent engineering flows'20005,956,257'Automated optimization of hierarchical netlists'19995,896,299'Method and a system for fixing hold time violations in hierarchical designs'19995,841,663'Apparatus and method for synthesizing integrated circuits using parameterized HDL modules'19985,825,658'Method and a system for specifying and automatically analyzing multiple clock timing constraints in a VLSI circuit'19985,764,525'Method for improving the operation of a circuit through iterative substitutions and performance analyses of datapath cells'19985,751,596'Automated system and method for identifying critical timing paths in integrated circuit layouts for use with automated circuit layout system'19985,726,902'Method and apparatus for characterizing timing behavior of datapaths for integrated circuit design and fabrication'19985,638,290'Method for eliminating a false critical path in a logic circuit'19975,633,803'Process for the processing of specification data of logic functions of an application-specific integrated circuit'19975,426,591'Apparatus and method for improving the timing performance of a circuit'19955,396,435'Automated circuit design system and method for reducing critical path delay times'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2001Patents assigned to VLSI TECHNOLOGY INC (13)· patent assignee history
1995–2021Based in Antibes, FR· patent location history
1998–2002Based in Antibe, FR· patent location history
1998Based in Antibon, FR· patent location history
2000Based in Antibos, FR· patent location history
2002–2021Patents assigned to CADENCE DESIGN SYSTEMS INC (70)· patent assignee history
2012–2015Patents assigned to GINETTI ARNOLD (10)· patent assignee history
2013Patents assigned to ARORA RAJAN (2)· patent assignee history
2014Patents assigned to O'RIORDAN DONALD J (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CADENCE DESIGN SYSTEMS INC | 70 | 2002–2021 |
| VLSI TECHNOLOGY INC | 13 | 1995–2001 |
| GINETTI ARNOLDself | 10 | 2012–2015 |
| ARORA RAJAN | 2 | 2013 |
| O'RIORDAN DONALD J | 2 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Antibes, FR | 78 | 1995–2021 |
| Antibe, FR | 4 | 1998–2002 |
| Antibos, FR | 1 | 2000 |
| Antibon, FR | 1 | 1998 |