Inventor
Allan T. Mitchell
Inventor
Garland, TX, US
Overview
Patents· 50 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices34%
H10BElectronic memory devices27%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
G11CStatic stores8%
H01LSemiconductor devices6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
A01GHorticulture2%
B81BMicrostructural devices or systems, e.g. micromechanical devices2%
G01NInvestigating or analysing materials by determining their chemical or physical properties2%
PatentTitleYear
10,192,998Analog floating-gate atmometer20199,882,065'Analog floating-gate atmometer'20189,466,572'Ultraviolet energy shield for non-volatile charge storage memory'20169,406,621'Ultraviolet energy shield for non-volatile charge storage memory'20169,257,440'Non-volatile anti-fuse with consistent rupture'20169,064,903'Analog floating-gate memory manufacturing process implementing n-channel and p-channel MOS transistors'20158,981,445'Analog floating-gate memory with N-channel and P-channel MOS transistors'20158,908,412'Array architecture for reduced voltage, low power, single poly EEPROM'20148,748,235'Non-volatile anti-fuse with consistent rupture'20148,729,616'Low leakage capacitor for analog floating-gate integrated circuits'20148,716,083'Unitary floating-gate electrode with both N-type and P-type gates'20148,679,929'On current in one-time-programmable memory cells'20148,664,706'Current in one-time-programmable memory cells'20148,593,846'Analog floating gate charge loss compensation circuitry and method'20138,558,296'Low leakage capacitor for analog floating-gate integrated circuits'20138,546,222'Electrically erasable programmable non-volatile memory'20138,258,586'Non-volatile anti-fuse with consistent rupture'20128,178,915'Unitary floating-gate electrode with both N-type and P-type gates'20128,174,884'Low power, single poly EEPROM cell with voltage divider'20126,306,718'Method of making polysilicon resistor having adjustable temperature coefficients'20015,306,935'Method of forming a nonvolatile stacked memory'19945,225,363'Trench capacitor DRAM cell and method of manufacture'19935,168,334'Non-volatile semiconductor memory'19925,159,570'Four memory state EEPROM'19925,156,990'Floating-gate memory cell with tailored doping profile'19925,143,860'High density EPROM fabricaiton method having sidewall floating gates'19925,120,672'Fabricating a single level merged EEPROM cell having an ONO memory stack substantially spaced from the source region'19925,114,530'Interlevel dielectric process'19925,105,245'Trench capacitor DRAM cell with diffused bit lines adjacent to a trench'19925,084,418'Method of making an array device with buried interconnects'19925,053,839'Floating gate memory cell and device'19915,045,490'Method of making a pleated floating gate trench EPROM'19915,036,375'Floating-gate memory cell with tailored doping profile'19915,028,553'Method of making fast, trench isolated, planar flash EEPROMS with silicided bitlines'19914,980,309'Method of making high density EEPROM'19904,979,005'Floating-gate memory cell with tailored doping profile'19904,979,004'Floating gate memory cell and device'19904,977,439'Buried multilevel interconnect system'19904,951,103'Fast, trench isolated, planar flash EEPROMS with silicided bitlines'19904,905,062'Planar famos transistor with trench isolation'19904,878,996'Method for reduction of filaments between electrodes'19894,853,895'EEPROM including programming electrode extending through the control gate electrode'19894,839,705'X-cell EEPROM array'19894,833,514'Planar FAMOS transistor with sealed floating gate and DCS+N.sub.2 O oxide'19894,829,019'Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment'19894,806,201'Use of sidewall oxide to reduce filaments'19894,799,992'Interlevel dielectric fabrication process'19894,749,443'Sidewall oxide to reduce filaments'19884,713,142'Method for fabricating EPROM array'19874,597,060'EPROM array and method for fabricating'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986–2019Patents assigned to TEXAS INSTRUMENTS INC (48)· patent assignee history
1986–1994Based in Garland, TX, US· patent location history
1988–1989Based in Dallas, TX, US· patent location history
1990–2016Patents assigned to MITCHELL ALLAN T (13)· patent assignee history
2001–2019Based in Heath, TX, US· patent location history
2012–2015Patents assigned to KHAN IMRAN MAHMOOD (4)· patent assignee history
2012–2016Patents assigned to JARREAU KEITH (3)· patent assignee history
2012–2015Patents assigned to WU MICHAEL A (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 48 | 1986–2019 |
| MITCHELL ALLAN Tself | 13 | 1990–2016 |
| KHAN IMRAN MAHMOOD | 4 | 2012–2015 |
| JARREAU KEITH | 3 | 2012–2016 |
| WU MICHAEL A | 3 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Garland, Texas, US | 28 | 1986–1994 |
| Heath, Texas, US | 20 | 2001–2019 |
| Dallas, Texas, US | 2 | 1988–1989 |