Inventor
Geeng-Chuan Chern
Inventor
Cupertino, CA, US
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices36%
H10BElectronic memory devices21%
H01LSemiconductor devices12%
G11CStatic stores11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
G05FSystems for regulating electric or magnetic variables1%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy1%
H03KPulse technique1%
PatentTitleYear
11,114,442Semiconductor memory device with shallow buried capacitor and fabrication method thereof202111,114,140One time programmable (OTP) bits for physically unclonable functions202111,088,155Method for fabricating split-gate non-volatile memory202111,074,985One-time programmable memory device and method for operating the same202111,049,947Non-volatile memory and manufacturing method for the same202110,971,595MOFSET and method of fabricating same202110,957,776Method of fabricating MOSFET202110,950,601Current source using emitter region as base region isolation structure202110,916,664Non-volatile memory and manufacturing method for the same202110,854,758Non-volatile memory and manufacturing method for the same202010,726,894Non-volatile memory cell, array and fabrication method202010,636,801Split-gate non-volatile memory and fabrication method thereof20209,595,335'Memory device and systems and methods for selecting memory cells in the memory device'20179,502,581'Non-volatile floating gate memory cells'20169,142,306'Selecting memory cells using source lines'20157,974,136'Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio'20117,964,933'Integrated circuit including power diode'20117,701,248'Storage element for controlling a logic circuit, and a logic device having an array of such storage elements'20107,668,013'Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio'20107,250,668'Integrated circuit including power diode'20077,084,453'Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric'20067,008,846'Non-volatile floating gate memory cell with floating gates formed as spacers, and an array thereof, and a method of manufacturing'20066,979,861'Power device having reduced reverse bias leakage current'20056,967,372'Semiconductor memory array of floating gate memory cells with vertical control gate sidewalls and insulation spacers'20056,765,264'Method of fabricating power rectifier device to vary operating parameters and resulting device'20046,750,090'Self aligned method of forming a semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges, and a memory array made thereby'20046,743,703'Power diode having improved on resistance and breakdown voltage'20046,706,592'Self aligned method of forming a semiconductor array of non-volatile memory cells'20046,624,030'Method of fabricating power rectifier device having a laterally graded P-N junction for a channel region'20036,563,167'Semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges'20036,537,860'Method of fabricating power VLSI diode devices'20036,515,330'Power device having vertical current path with enhanced pinch-off for current limiting'20036,498,367'Discrete integrated circuit rectifier device'20026,448,160'Method of fabricating power rectifier device to vary operating parameters and resulting device'20026,426,541'Schottky diode having increased forward current with improved reverse bias characteristics and method of fabrication'20026,420,225'Method of fabricating power rectifier device'20026,404,033'Schottky diode having increased active surface area with improved reverse bias characteristics and method of fabrication'20026,399,996'Schottky diode having increased active surface area and method of fabrication'2002RE035094'Fabrication process for programmable and erasable MOS memory device'19955,081,054'Fabrication process for programmable and erasable MOS memory device'19925,066,992'Programmable and erasable MOS memory device'19914,859,619'EPROM fabrication process forming tub regions for high voltage devices'19894,833,096'EEPROM fabrication process'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989–2017Patents assigned to ATMEL CORP (8)· patent assignee history
1989Based in Campbell, CA, US· patent location history
1991–2021Based in Cupertino, CA, US· patent location history
2002–2005Patents assigned to APD SEMICONDUCTOR INC (10)· patent assignee history
2003–2011Patents assigned to SILICON STORAGE TECH INC (9)· patent assignee history
2020–2021Patents assigned to NEXCHIP SEMICONDUCTOR CO LTD (6)· patent assignee history
2020–2021Based in Anhui, CN· patent location history
2020Based in Hefei, CN· patent location history
2021Patents assigned to HEFECHIP CORPORATION LTD (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APD SEMICONDUCTOR INC | 10 | 2002–2005 |
| SILICON STORAGE TECH INC | 9 | 2003–2011 |
| ATMEL CORP | 8 | 1989–2017 |
| NEXCHIP SEMICONDUCTOR CO LTD | 6 | 2020–2021 |
| HEFECHIP CORPORATION LTD | 3 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 32 | 1991–2021 |
| Anhui, CN | 7 | 2020–2021 |
| Hefei, CN | 2 | 2020 |
| Campbell, California, US | 2 | 1989 |