Inventor
Avinash Sodani
Inventor
Portland, OR, US
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing73%
G06NComputing arrangements based on specific computational models19%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
G05BControl or regulating systems in general2%
G11CStatic stores2%
H04NPictorial communication, e.g. television2%
PatentTitleYear
11,086,633Single instruction set architecture (ISA) format for multiple ISAS in machine learning inference engine202111,029,963Architecture for irregular operations in machine learning inference engine202111,016,801Architecture to support color scheme-based synchronization for machine learning202110,997,510Architecture to support tanh and sigmoid operations for inference acceleration in machine learning202110,970,080Systems and methods for programmable hardware architecture for machine learning202110,929,760Architecture for table-based mathematical operations for inference acceleration in machine learning202110,929,779Architecture to support synchronization between core and inference engine for machine learning202110,929,778Address interleaving for machine learning202110,896,045Architecture for dense operations in machine learning inference engine202110,891,136Data transmission between memory and on chip memory of inference engine for machine learning via a single data gathering instruction202110,824,433Array-based inference engine for machine learning202010,346,300Providing multiple memory modes for a processor including internal memory201910,275,001Thermal throttling of electronic devices201910,102,129Minimizing snoop traffic locally and across cores on a chip multi-core fabric20189,898,351'Method and apparatus for user-level thread synchronization with a monitor and MWAIT architecture'20189,886,396'Scalable event handling in multi-threaded processor cores'20189,836,399Mechanism to avoid hot-L1/cold-L2 events in an inclusive L2 cache using L1 presence bits for victim selection bias20179,733,939'Physical reference list for tracking physical register sharing'20179,720,827'Providing multiple memory modes for a processor including internal memory'20179,594,648'Controlling non-redundant execution in a redundant multithreading (RMT) processor'20179,524,191'Apparatus including a stall counter to bias processing element selection, and masks to allocate reservation unit entries to one or more processing elements'20169,507,596'Instruction and logic for prefetcher throttling based on counts of memory accesses to data sources'20169,081,688'Obtaining data for redundant multithreading (RMT) execution'20158,825,989'Technique to perform three-source operations'20148,793,689'Redundant multithreading processor'20148,589,663'Technique to perform three-source operations'20138,521,993'Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor'20138,504,804'Managing multiple threads in a single pipeline'20138,438,369'Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor'20138,402,253'Managing multiple threads in a single pipeline'20137,721,076'Tracking an oldest processor event using information stored in a register and queue entry'20107,711,898'Register alias table cache to map a logical register to a physical register'20107,600,103'Speculatively scheduling micro-operations after allocation'20097,562,206'Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions'20097,529,913'Late allocation of registers'20097,502,912'Method and apparatus for rescheduling operations in a processor'20097,475,225'Method and apparatus for microarchitecture partitioning of execution clusters'20097,457,938'Staggered execution stack for vector processing'20087,404,065'Flow optimization and prediction for VSSE memory operations'20087,363,430'Determination of cache entry for future operation'20087,272,701'Method and apparatus for limiting ports in a register alias table having high-bandwidth and low-bandwidth structures'20077,174,428'Method and system for transforming memory location references in instructions'20075,845,103'Computer with dynamic instruction reuse'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998Based in Madison, WI, US· patent location history
2007–2019Patents assigned to INTEL CORP (31)· patent assignee history
2007–2019Based in Portland, OR, US· patent location history
2007–2009Based in Hillsboro, OR, US· patent location history
2013–2017Patents assigned to SODANI AVINASH (9)· patent assignee history
2013–2016Patents assigned to FARCY ALEXANDRE (6)· patent assignee history
2020–2021Patents assigned to MARVELL ASIA PTE LTD (11)· patent assignee history
2020–2021Patents assigned to CAVIUM LLC (5)· patent assignee history
2020–2021Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 31 | 2007–2019 |
| MARVELL ASIA PTE LTD | 11 | 2020–2021 |
| SODANI AVINASHself | 9 | 2013–2017 |
| FARCY ALEXANDRE | 6 | 2013–2016 |
| CAVIUM LLC | 5 | 2020–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 26 | 2007–2019 |
| San Jose, California, US | 11 | 2020–2021 |
| Hillsboro, OR, US | 5 | 2007–2009 |
| Madison, WI, US | 1 | 1998 |