Inventor
Masaru Uesugi
Inventor
Tokyo, JP
Overview
Patents· 9 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores78%
G05FSystems for regulating electric or magnetic variables11%
H03KPulse technique11%
PatentTitleYear
5,278,799'Semiconductor memory circuit'19945,272,665'Semiconductor memory with improved sense amplifier layout'19935,216,634'Semiconductor memory device'19935,140,556'Semiconductor memory circuit having dummy cells connected to twisted bit lines'19925,103,158'Reference voltage generating circuit'19925,058,073'CMOS RAM having a complementary channel sense amplifier'19915,001,669'Semiconductor memory circuit having dummy cells connected to twisted bit lines'19914,763,304'Semiconductor random access memory device having switchable input and output bit forms'19884,417,163'Buffer circuits'1983Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1983–1994Patents assigned to OKI ELECTRIC IND CO LTD (9)· patent assignee history
1983Patents assigned to NIPPON TELEGRAPH & TELEPHONE (1)· patent assignee history
1983–1994Based in Tokyo, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| OKI ELECTRIC IND CO LTD | 9 | 1983–1994 |
| NIPPON TELEGRAPH & TELEPHONE | 1 | 1983 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 9 | 1983–1994 |