Inventor

DER-CHYANG YEH

Inventor
TW

Overview

76→
Patents
2021–2026
Patent span
Electricity
Primary field (CPC H)

Patents· 76 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary
H01LSemiconductor devices37%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1037%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10DInorganic electric semiconductor devices4%
H10HInorganic light-emitting semiconductor devices having potential barriers2%
H05KPrinted circuits2%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light0%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation0%
PatentTitleYear
12,599,029Package structure and method of forming the same202612,575,433Semiconductor package and method of manufacturing the same202612,557,698Package and manufacturing method thereof202612,431,417Semiconductor package and method of manufacturing the same202512,394,758Packages with metal line crack prevention design202512,368,280Semiconductor device and method202512,347,749Semiconductor packages202512,341,104Methods of manufacturing semiconductor devices202512,327,819Devices employing thermal and mechanical enhanced layers and methods of forming same202512,327,815Integrated circuit package and method of forming the same202512,322,726Method of forming an integrated circuit package having a padding layer on a carrier202512,211,782Semiconductor package dielectric susbtrate including a trench202512,191,224Semiconductor package and manufacturing method thereof202512,170,207Stacked semiconductor devices and methods of forming same202412,159,853Package structure including IPD and method of forming the same202412,142,524Via for component electrode connection202412,087,745Package structure and manufacturing method thereof202412,062,602Semiconductor package and method of manufacturing the same202412,051,616Wafer level chip scale packaging intermediate structure apparatus and method202412,033,949Package structure with bridge die laterally wrapped by insulating encapsulant and surrounded by through vias and method of forming the package structure202412,020,953Fan-out structure and method of fabricating the same202412,009,335Structure and method of forming a joint assembly202411,984,405Pad structure design in fan-out package202411,961,796Semiconductor package dielectric substrate including a trench202411,961,800Via for semiconductor device connection and methods of forming the same202411,955,401Package structure202411,935,836Semiconductor devices202411,862,606Packages with metal line crack prevention design202411,854,994Redistribution structure for integrated circuit package and method of forming same202311,848,271Redistribution layer structures for integrated circuit package202311,842,983Semiconductor structure202311,837,587Package structure and manufacturing method thereof202311,823,912Stacked semiconductor devices and methods of forming same202311,804,475Semiconductor package for thermal dissipation202311,742,298Alignment mark design for packages202311,728,249Semiconductor package and method202311,721,559Integrated circuit package pad and methods of forming202311,715,727Packages and methods of forming packages202311,682,654Semiconductor structure having a sensor device and method of manufacturing the same202311,664,322Multi-stacked package-on-package structures202311,652,063Semiconductor package and method of forming the same202311,646,220Raised via for terminal connections on different planes202311,631,611Wafer level chip scale packaging intermediate structure apparatus and method202311,626,296Fan-out structure and method of fabricating the same202311,626,341Package structure202311,612,057Opening in the pad for bonding integrated passive device in InFO package202311,594,520Semiconductor package for thermal dissipation202311,587,900Package structure including IPD and method of forming the same202311,581,250Package with metal-insulator-metal capacitor and method of manufacturing the same202311,532,567Electric magnetic shielding structure in packages202211,515,229Semiconductor package and manufacturing method thereof202211,508,695Redistribution layers in semiconductor packages and methods of forming same202211,502,032Chip package and method of fabricating the same202211,482,497Package structure including a first die and a second die and a bridge die and method of forming the package structure202211,470,720Opening in the pad for bonding integrated passive device in InFO package202211,469,138Via for coupling attached component upper electrode to substrate202211,469,218Devices employing thermal and mechanical enhanced layers and methods of forming same202211,450,612Semiconductor devices and methods of manufacturing the same202211,444,034Redistribution structure for integrated circuit package and method of forming same202211,444,057Package structures and methods of forming202211,444,020Via for semiconductor device connection and methods of forming the same202211,430,670Stacked semiconductor devices and methods of forming same202211,424,189Pad structure design in fan-out package202211,373,969Semiconductor package and method of forming the same202211,355,468Structure and method of forming a joint assembly202211,342,196Integrated circuit package pad and methods of forming202211,335,658Multi-chip package and method of formation202211,289,398Package structure and manufacturing method thereof202211,251,071Raised via for terminal connections on different planes202211,217,570Package structure and manufacturing method thereof202211,201,142Semiconductor package, package on package structure and method of froming package on package structure202111,189,603Semiconductor packages and methods of forming same202111,177,238Semiconductor structure202111,177,142Method for dicing integrated fan-out packages without seal rings202111,158,619Redistribution layers in semiconductor packages and methods of forming same202111,152,323Package with UBM and methods of forming2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (75)· patent assignee history
2021–2026Based in TW· patent location history
2026Patents assigned to TAIWAN SEMICONDUCTOR MFG COMPANY LTD (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TAIWAN SEMICONDUCTOR MFG CO LTD752021–2026
TAIWAN SEMICONDUCTOR MFG COMPANY LTD12026
Locations
LocationPatentsSpan
TW762021–2026