Inventor
Fei Wang
Inventor
San Jose, CA, US
Overview
Patents· 196 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1030%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10BElectronic memory devices8%
H10DInorganic electric semiconductor devices4%
H01LSemiconductor devices4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form2%
D21HPulp compositions2%
Y10TTechnical subjects covered by former us classification2%
D04HMaking textile fabrics, e.g. from fibres or filamentary material1%
PatentTitleYear
10,874,279Compressible pre-moistened fibrous structures202010,833,013Memory device interconnects and method of manufacture202010,833,009Memory device interconnects and method of manufacture202010,745,865Creped fibrous structures202010,745,864Differential pillow height fibrous structures202010,711,395Textured fibrous structures202010,714,339Selectively deposited parylene masks and methods related thereto202010,707,121Solid state memory device, and manufacturing method thereof202010,683,878Spatially controllable eductor for managing solid additives and processes using same202010,636,705High pressure annealing of metal gate structures202010,576,718Heat sealable multilayer packaging film with improved opacity202010,543,488Discretizer and method of using same202010,538,881Fibrous structures202010,497,573Selective atomic layer etching of semiconductor materials201910,478,865Fibrous structures comprising regions having different solid additive levels201910,428,464Fibrous structures comprising three or more regions201910,428,463Fibrous structures comprising regions having different micro-CT intensive property values and associated transition slopes201910,392,691Semiconductor silicon-germanium thin film preparation method201910,378,133Article of manufacture making system201910,227,477Glass mat for roofing products201910,195,155Drug carrier for tumor-specific targeted drug delivery and use thereof201910,186,716Non-aqueous flow cell comprising a polyurethane separator20199,875,907Self-aligned shielding of silicon oxide20189,859,128'Self-aligned shielding of silicon oxide'20189,721,789'Saving ion-damaged spacers'20179,685,655'Complex showerhead coating apparatus with electrospray for lithium ion battery'20179,637,837'Solution-based synthesis of doped ZnO nanostructures'20179,617,734'Glass mat for roofing products'20179,576,815'Gas-phase silicon nitride selective etch'20179,567,689'Method of growing nanostructured single crystal silver on active carbon'20179,343,666'Damascene metal-insulator-metal (MIM) device with improved scaleability'20169,331,331'Water-based binder for high voltage cathode material for Li-ion battery'20169,200,413'Composite tack film'20159,184,315'Photoelectric materials and preparation thereof'20159,058,993'Methods for making large-area, free-standing metal oxide films'20159,041,172'Semiconductor device for restraining creep-age phenomenon and fabricating method thereof'20158,912,093'Die seal layout for VFTL dual damascene in a semiconductor device'20148,882,385'Composite tack film'20148,716,111'Method for manufacturing trench type superjunction device and trench type superjunction device'20148,669,597'Memory device interconnects and method of manufacturing'20148,576,162'Manufacturing processes of backplane for segment displays'20138,546,882'Terminal structure for superjunction device and method of manufacturing the same'20138,502,218'Large-area, free-standing metal oxide films and transistors made therefrom'20138,486,767'Interconnects with improved electromigration reliability'20138,441,432'Display cell structure and electrode protecting layer compositions'20138,252,922'Method for crystallizing sucralose'20128,232,175'Damascene metal-insulator-metal (MIM) device with improved scaleability'20128,114,756'Method and manufacture for high voltage gate oxide formation after shallow trench isolation formation'20128,089,113'Damascene metal-insulator-metal (MIM) device'20128,035,153'Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications'20117,989,956'Interconnects with improved electromigration reliability'20117,927,711'Durable layer composition for in-mold decoration'20117,910,205'Release layer for in-mold decoration'20117,884,203'Method of sucralose synthesis yield'20117,880,958'Display cell structure and electrode protecting layer compositions'20117,838,642'Process for the preparation of sucralose by the deacylation of trichlorosucrose-6-ethyl ester'20107,838,668'Method for crystallizing sucralose'20107,776,682'Ordered porosity to direct memory element formation'20107,732,276'Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications'20107,622,389'Selective contact formation using masking and resist patterning techniques'20097,385,460'Combined electrostatic and optical waveguide based microfluidic chip systems and methods'20087,279,410'Method for forming inlaid structures for IC interconnections'20077,256,499'Ultra low dielectric constant integrated circuit system'20077,232,765'Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias and memory element structures'20077,208,418'Sealing sidewall pores in low-k dielectrics'20077,132,363'Stabilizing fluorine etching of low-k materials'20067,038,320'Single damascene integration scheme for preventing copper contamination of dielectric layer'20067,001,840'Interconnect with multiple layers of conductive material with grain boundary between the layers'20066,939,793'Dual damascene integration scheme for preventing copper contamination of dielectric layer'20056,878,622'Method for forming SAC using a dielectric as a BARC and FICD enlarger'20056,833,625'Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect'20046,770,559'Method of forming wiring by implantation of seed layer material'20046,768,204'Self-aligned conductive plugs in a semiconductor device'20046,767,827'Method for forming dual inlaid structures for IC interconnections'20046,756,303'Diffusion barrier and method for its production'20046,756,300'Method for forming dual damascene interconnect structure'20046,740,566'Ultra-thin resist shallow trench process using high selectivity nitride etch'20046,699,792'Polymer spacers for creating small geometry space and method of manufacture thereof'20046,689,684'Cu damascene interconnections using barrier/capping layer'20046,677,679'Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers'20046,670,265'Low K dielectic etch in high density plasma etcher'20036,664,185'Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect'20036,660,619'Dual damascene metal interconnect structure with dielectric studs'20036,656,830'Dual damascene with silicon carbide middle etch stop layer/ARC'20036,632,707'Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning'20036,610,608'Plasma etching using combination of CHF3 and CH3F'20036,603,206'Slot via filled dual damascene interconnect structure without middle etch stop layer'20036,599,839'Plasma etch process for nonhomogenous film'20036,586,842'Dual damascene integration scheme for preventing copper contamination of dielectric layer'20036,583,046'Post-treatment of low-k dielectric for prevention of photoresist poisoning'20036,577,009'Use of sic for preventing copper contamination of dielectric layer'20036,562,683'Bit-line oxidation by removing ONO oxide prior to bit-line implant'20036,544,885'Polished hard mask process for conductor layer patterning'20036,537,881'Process for fabricating a non-volatile memory device'20036,534,397'Pre-treatment of low-k dielectric for prevention of photoresist poisoning'20036,528,390'Process for fabricating a non-volatile memory device'20036,528,409'Interconnect structure formed in porous dielectric material with minimized degradation and electromigration'20036,524,947'Slotted trench dual inlaid structure and method of forming thereof'20036,521,524'Via filled dual damascene structure with middle stop layer and method for making the same'20036,518,185'Integration scheme for non-feature-size dependent cu-alloy introduction'20036,514,860'Integration of organic fill for dual damascene process'20036,509,229'Method for forming self-aligned contacts using consumable spacers'20036,492,272'Carrier gas modification for use in plasma ashing of photoresist'20026,486,029'Integration of an ion implant hard mask structure into a process for fabricating high density memory cells'20026,482,699'Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process'20026,475,915'Ono etch using CL2/HE chemistry'20026,475,847'Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer'20026,475,929'Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant'20026,472,317'Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers'20026,465,340'Via filled dual damascene structure with middle stop layer and method for making the same'20026,465,343'Method for forming backend interconnect with copper etching and ultra low-k dielectric materials'20026,465,889'Silicon carbide barc in dual damascene processing'20026,465,361'Method for preventing damage of low-k dielectrics during patterning'20026,454,916'Selective electroplating with direct contact chemical polishing'20026,444,573'Method of making a slot via filled dual damascene structure with a middle stop layer'20026,444,530'Process for fabricating an integrated circuit with a self-aligned contact'20026,440,640'Thin resist with transition metal hard mask for via etch application'20026,436,766'Process for fabricating high density memory cells using a polysilicon hard mask'20026,429,116'Method of fabricating a slot dual damascene structure without middle stop layer'20026,424,039'Dual damascene process using sacrificial spin-on materials'20026,423,612'Method of fabricating a shallow trench isolation structure with reduced topography'20026,420,752'Semiconductor device with self-aligned contacts using a liner oxide layer'20026,416,620'Method of repulping repulpable and recyclable moisture resistant coated articles'20026,417,090'Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer'20026,399,480'Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction'20026,400,030'Self-aligning vias for semiconductors'20026,399,446'Process for fabricating high density memory cells using a metallic hard mask'20026,391,766'Method of making a slot via filled dual damascene structure with middle stop layer'20026,383,919'Method of making a dual damascene structure without middle stop layer'20026,380,091'Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer'20026,376,308'Process for fabricating an EEPROM device having a pocket substrate region'20026,376,389'Method for eliminating anti-reflective coating in semiconductors'20026,372,631'Method of making a via filled dual damascene structure without middle stop layer'20026,372,635'Method for making a slot via filled dual damascene low k interconnect structure without middle stop layer'20026,365,505'Method of making a slot via filled dual damascene structure with middle stop layer'20026,362,052'Use of an etch to reduce the thickness and around the edges of a resist mask during the creation of a memory cell'20026,359,307'Method for forming self-aligned contacts and interconnection lines using dual damascene techniques'20026,358,362'Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process'20026,355,575'Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern'20026,348,406'Method for using a low dielectric constant layer as a semiconductor anti-reflective coating'20026,348,379'Method of forming self-aligned contacts using consumable spacers'20026,329,701'Semiconductor device comprising copper interconnects with reduced in-line diffusion'20016,326,268'Method of fabricating a MONOS flash cell using shallow trench isolation'20016,319,834'Method and apparatus for improved planarity metallization by electroplating and CMP'20016,312,874'Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials'20016,313,018'Process for fabricating semiconductor device including antireflective etch stop layer'20016,309,955'Method for using a CVD organic barc as a hard mask during via etch'20016,309,926'Thin resist with nitride hard mask for gate etch application'20016,306,713'Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer'20016,306,560'Ultra-thin resist and SiON/oxide hard mask for metal etch'20016,303,949'Method and system for providing electrical insulation for local interconnect in a logic circuit'20016,297,167'In-situ etch of multiple layers during formation of local interconnects'20016,297,143'Process for forming a bit-line in a MONOS device'20016,291,887'Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer'20016,271,087'Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects'20016,261,952'Method of forming copper interconnects with reduced in-line diffusion'20016,255,735'Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers'20016,242,305'Process for fabricating a bit-line using buried diffusion isolation'20016,235,628'Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer'20016,211,071'Optimized trench/via profile for damascene filling'20016,207,502'Method of using source/drain nitride for periphery field oxide and bit-line oxide'20016,207,576'Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide etch stop layer'20016,207,577'Self-aligned dual damascene arrangement for metal interconnection with oxide dielectric layer and low k dielectric constant layer'20016,200,907'Ultra-thin resist and barrier metal/oxide hard mask for metal etch'20016,184,128'Method using a thin resist mask for dual damascene stop layer etch'20016,171,763'Ultra-thin resist and oxide/nitride hard mask for metal etch'20016,168,993'Process for fabricating a semiconductor device having a graded junction'20016,165,695'Thin resist with amorphous silicon hard mask for via etch application'20006,162,587'Thin resist with transition metal hard mask for via etch application'20006,156,658'Ultra-thin resist and silicon/oxide hard mask for metal etch'20006,156,643'Method of forming a dual damascene trench and borderless via structure'20006,153,514'Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer'20006,140,706'Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern utilizing multiple dielectric layers'20006,140,023'Method for transferring patterns created by lithography'20006,127,070'Thin resist with nitride hard mask for via etch application'20006,124,201'Method for manufacturing semiconductors with self-aligning vias'20006,121,663'Local interconnects for improved alignment tolerance and size reduction'20006,121,150'Sputter-resistant hardmask for damascene trench/via formation'20006,121,149'Optimized trench/via profile for damascene filling'20006,117,781'Optimized trench/via profile for damascene processing'20006,117,782'Optimized trench/via profile for damascene filling'20006,114,235'Multipurpose cap layer dielectric'20006,107,208'Nitride etch using N.sub.2 /Ar/CHF.sub.3 chemistry'20006,086,777'Tantalum barrier metal removal by using CF.sub.4 /o.sub.2 plasma dry etch'20006,060,380'Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication'20006,060,328'Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process'20006,057,239'Dual damascene process using sacrificial spin-on materials'20006,054,384'Use of hard masks during etching of openings in integrated circuits for high etch selectivity'20006,040,619'Semiconductor device including antireflective etch stop layer'20006,020,269'Ultra-thin resist and nitride/oxide hard mask for metal etch'20005,956,610'Method and system for providing electrical insulation for local interconnect in a logic circuit'19995,952,246'Nitride selective, anisotropic Cl.sub.2 /He etch process'19995,920,796'In-situ etch of BARC layer during formation of local interconnects'19995,907,781'Process for fabricating an integrated circuit with a self-aligned contact'19995,895,269'Methods for preventing deleterious punch-through during local interconnect formation'19995,376,573'Method of making a flash EPROM device utilizing a single masking step for etching and implanting source regions within the EPROM core and redundancy areas'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2013Patents assigned to ADVANCED MICRO DEVICES INC (136)· patent assignee history
1999–2020Based in San Jose, CA, US· patent location history
2009–2014Patents assigned to SPANSION LLC (9)· patent assignee history
2010–2012Based in Nanjing, CN· patent location history
2011–2020Based in Fremont, CA, US· patent location history
2012–2016Patents assigned to WANG FEI (15)· patent assignee history
2014–2019Based in Stoneham, MA, US· patent location history
2016–2020Patents assigned to APPLIED MATERIALS INC (9)· patent assignee history
2019–2020Patents assigned to PROCTER & GAMBLE (12)· patent assignee history
2019–2020Based in Mason, OH, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 136 | 1994–2013 |
| WANG FEIself | 15 | 2012–2016 |
| PROCTER & GAMBLE | 12 | 2019–2020 |
| APPLIED MATERIALS INC | 9 | 2016–2020 |
| SPANSION LLC | 9 | 2009–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 146 | 1999–2020 |
| Fremont, California, US | 13 | 2011–2020 |
| Mason, OH, US | 11 | 2019–2020 |
| Stoneham, Massachusetts, US | 4 | 2014–2019 |
| Nanjing, CN | 4 | 2010–2012 |