Inventor

Louis N. Hutter

Inventor

Richardson, TX, US

Overview

1989–2007

Patent span

Electricity

Primary field (CPC H)

Patents· 46 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices57%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests14%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%

H10BElectronic memory devices4%

Y10TTechnical subjects covered by former us classification1%

PatentTitleYear

7,279,738'Semiconductor device with an analog capacitor'2007 6,979,615'System and method for forming a semiconductor with an analog capacitor using fewer structure steps'2005 6,737,326'Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect'2004 6,706,635'Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis'2004 6,683,380'Integrated circuit with bonding layer over active circuitry'2004 6,534,364'Tunnel diode layout for an EEPROM cell for protecting the tunnel diode region'2003 6,432,791'Integrated circuit capacitor and method'2002 6,424,005'LDMOS power device with oversized dwell'2002 6,396,109'Isolated NMOS transistor fabricated in a digital BiCMOS process'2002 6,352,887'Merged bipolar and CMOS circuit and method'2002 6,284,669'Power transistor with silicided gate and contacts'2001 6,284,617'Metalization outside protective overcoat for improved capacitors and inductors'2001 6,236,101'Metallization outside protective overcoat for improved capacitors and inductors'2001 6,153,451'Transistor with increased operating voltage and method of fabrication'2000 6,144,100'Integrated circuit with bonding layer over active circuitry'2000 6,033,946'Method for fabricating an isolated NMOS transistor on a digital BiCMOS process'2000 6,025,231'Self aligned DMOS transistor and method of fabrication'2000 5,929,506'Isolated vertical PNP transistor and methods for making same in a digital BiCMOS process'1999 5,880,002'Method for making isolated vertical PNP transistor in a digital BiCMOS process'1999 5,825,065'Low voltage DMOS transistor'1998 5,719,421'DMOS transistor with low on-resistance and method of fabrication'1998 5,702,959'Method for making an isolated vertical transistor'1997 5,614,755'High voltage Shottky diode'1997 5,576,233'Method for making an EEPROM with thermal oxide isolated floating gate'1996 5,574,298'Substrate contact for gate array base cell and method of forming same'1996 5,554,873'Semiconductor device having polysilicon resistor with low temperature coefficient'1996 5,527,722'Method of fabrication of a semiconductor device having high-and low-voltage MOS transistors'1996 5,528,064'Structure for protecting integrated circuits from electro-static discharge'1996 5,489,547'Method of fabricating semiconductor device having polysilicon resistor with low temperature coefficient'1996 5,472,887'Method of fabricating semiconductor device having high-and low-voltage MOS transistors'1995 5,455,447'Vertical PNP transistor in merged bipolar/CMOS technology'1995 5,436,179'Semiconductor process for manufacturing semiconductor devices with increased operating voltages'1995 5,408,125'Semiconductor process for manufacturing semiconductor device with increased operating voltages'1995 5,330,922'Semiconductor process for manufacturing semiconductor devices with increased operating voltages'1994 5,317,180'Vertical DMOS transistor built in an n-well MOS-based BiCMOS process'1994 5,296,393'Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods'1994 5,272,098'Vertical and lateral insulated-gate, field-effect transistors, systems and methods'1993 5,171,699'Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication'1992 5,057,443'Method for fabricating a trench bipolar transistor'1991 4,994,887'High voltage merged bipolar/CMOS technology'1991 4,980,747'Deep trench isolation with surface contact to substrate'1990 4,929,996'Trench bipolar transistor'1990 4,926,233'Merged trench bipolar-CMOS transistor fabrication process'1990 4,855,244'Method of making vertical PNP transistor in merged bipolar/CMOS technology'1989 4,819,052'Merged bipolar/CMOS technology using electrically active trench'1989 4,805,071'High voltage capacitor for integrated circuits'1989

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1989–2007Patents assigned to TEXAS INSTRUMENTS INC (45)· patent assignee history

1989–2003Based in Richardson, TX, US· patent location history

1996Patents assigned to TEXAS INSTR INCOPORATED (1)· patent assignee history

1996Based in Richarson, TX, US· patent location history

2002–2007Based in Plano, TX, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TEXAS INSTRUMENTS INC	45	1989–2007
TEXAS INSTR INCOPORATED	1	1996

Locations

Location	Patents	Span
Richardson, Texas, US	38	1989–2003
Plano, Texas, US	7	2002–2007
Richarson, Texas, US	1	1996