Inventor
VINODH GOPAL
Inventor
US
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing43%
H04LTransmission of digital information, e.g. telegraphic communication27%
H03MCoding14%
G06NComputing arrangements based on specific computational models4%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy4%
G11CStatic stores1%
H02JElectric power networks1%
H04WWireless communication networks1%
H10BElectronic memory devices1%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%
PatentTitleYear
12,572,355Modular addition instruction202612,537,666Efficient implementation of ZUC authentication202612,494,800Apparatus and method for constant detection during compress operations202512,483,515Application-to-application resource reservation schemes for precision networking202512,476,462Platform configuration based on availability of sustainable energy202512,443,458Efficient accelerator offload in multi-accelerator framework202512,443,409Conditional modular subtraction instruction202512,413,388Methods and apparatus to hash data202512,405,893Technology for early abort of compression acceleration202512,399,718Apparatuses, methods, and systems for hashing instructions202512,367,164Circuitry and methods for low-latency page decompression and compression acceleration202512,323,515Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality202512,255,921Efficient encryption in VPN sessions202512,242,851Verifying compressed stream fused with copy or transform operations202512,182,018Instruction and micro-architecture support for decompression on core202412,175,274Process-based multi-key total memory encryption202412,175,246Systems and methods for performing matrix compress and decompress instructions202412,130,738Compressed cache memory with decompress on fault202412,118,130Circuitry and methods for low-latency efficient chained decryption and decompression acceleration202412,081,649Error resilient cryptographic units and methods202412,074,618Flexible compression header and code generation202412,052,370Managing state in accelerators202412,028,094Application programming interface for fine grained low latency decompression within processor core202412,021,551Method and apparatus for efficient deflate decompression using content-addressable data structures202411,989,582Apparatus and method for low-latency decompression acceleration via a single job descriptor202411,955,995Apparatus and method for two-stage lossless data compression, and two-stage lossless data decompression202411,956,156Dynamic offline end-to-end packet processing based on traffic class202411,909,841System, apparatus and method for adaptive peer-to-peer communication with edge platform202411,900,108Rotate instructions that complete execution either without writing or reading flags202411,849,035Instructions and logic to provide SIMD SM4 cryptographic block cipher202311,748,103Systems and methods for performing matrix compress and decompress instructions202311,681,530Apparatuses, methods, and systems for hashing instructions202311,663,003Apparatus and method for executing Boolean functions via forming indexes to an immediate value from source register bits202311,595,055Methods and apparatus to parallelize data decompression202311,567,772Apparatuses, methods, and systems for hashing instructions202311,563,556Architecture and instruction set for implementing advanced encryption standard (AES)202311,550,582Method and apparatus to process SHA-2 secure hashing algorithm202311,531,542Addition instructions with independent carry chains202211,516,013Accelerator for encrypting or decrypting confidential data with additional authentication data202211,494,320Delayed link compression scheme202211,494,222Process-based multi-key total memory encryption202211,483,009Self-checking compression202211,455,257Ultra-secure accelerators202211,303,438Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality202211,258,459Methods and apparatus to parallelize data decompression202211,249,761Systems and methods for performing matrix compress and decompress instructions202211,243,836Supporting random access of compressed data202211,200,054Atomic-copy-XOR instruction for replacing data in a first cacheline with data from a second cacheline202111,188,335Apparatuses, methods, and systems for hashing instructions2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (47)· patent assignee history
2021–2026Based in US· patent location history
2022–2024Patents assigned to TAHOE RES LTD (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 47 | 2021–2026 |
| TAHOE RES LTD | 2 | 2022–2024 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 49 | 2021–2026 |