Inventor
Richard A. Hankins
Inventor
San Jose, CA, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing82%
G06TImage data processing or generation, in general9%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
PatentTitleYear
10,452,403Mechanism for instruction set based thread execution on a plurality of instruction sequencers20199,990,206Mechanism for instruction set based thread execution of a plurality of instruction sequencers20189,875,102Apparatus, system, and method for persistent user-level thread20189,766,891'Apparatus, system, and method for persistent user-level thread'20179,720,697'Mechanism for instruction set based thread execution on a plurality of instruction sequencers'20179,588,771'Instruction set architecture-based inter-sequencer communications with a heterogeneous resource'20179,459,874'Instruction set architecture-based inter-sequencer communications with a heterogeneous resource'20169,383,997'Apparatus, system, and method for persistent user-level thread'20169,069,605'Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention'20158,914,618'Instruction set architecture-based inter-sequencer communications with a heterogeneous resource'20148,887,174'Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers'20148,839,258'Load balancing for multi-threaded applications via asymmetric power throttling'20148,719,819'Mechanism for instruction set based thread execution on a plurality of instruction sequencers'20148,689,215'Structured exception handling for application-managed thread units'20148,607,235'Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention'20138,516,483'Transparent support for operating system services for a sequestered sequencer'20138,479,217'Apparatus, system, and method for persistent user-level thread'20138,205,200'Compiler-based scheduling optimization hints for user-level threads'20128,108,863'Load balancing for multi-threaded applications via asymmetric power throttling'20128,079,035'Data structure and management techniques for local user-level thread data'20118,074,274'User-level privilege management'20118,028,295'Apparatus, system, and method for persistent user-level thread'20118,010,969'Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers'20117,882,498'Method, system, and program of a compiler to parallelize source code'20117,810,083'Mechanism to emulate user-level multithreading on an OS-sequestered sequencer'20107,768,518'Enabling multiple instruction stream/multiple data stream extensions on microprocessors'20107,743,233'Sequencer address management'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2019Patents assigned to INTEL CORP (27)· patent assignee history
2010–2018Based in San Jose, CA, US· patent location history
2011–2017Patents assigned to WANG HONG (13)· patent assignee history
2011–2017Patents assigned to CHINYA GAUTHAM (9)· patent assignee history
2011–2014Patents assigned to HANKINS RICHARD A (9)· patent assignee history
2011–2017Patents assigned to SHEN JOHN (9)· patent assignee history
2016–2019Based in Santa Clara, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 27 | 2010–2019 |
| WANG HONG | 13 | 2011–2017 |
| CHINYA GAUTHAM | 9 | 2011–2017 |
| HANKINS RICHARD Aself | 9 | 2011–2014 |
| SHEN JOHN | 9 | 2011–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 22 | 2010–2018 |
| Santa Clara, California, US | 5 | 2016–2019 |