Inventor
Donald V. Perino
Inventor
Los Altos, CA, US
Overview
Patents· 50 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H05Kprimary
H05KPrinted circuits23%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
G06FElectric digital data processing16%
H01RElectrically-conductive connections13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
G11CStatic stores6%
H04LTransmission of digital information, e.g. telegraphic communication6%
H03KPulse technique3%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%
H04BTransmission3%
PatentTitleYear
RE043720'Integrated circuit device having stacked dies and impedance balanced transmission lines'20128,096,812'Chip socket assembly and chip file assembly for semiconductor chips'20128,076,759'Semiconductor package with a controlled impedance bus and method of forming same'20118,036,284'Method and apparatus for transmitting data with reduced coupling noise'20117,627,043'Method and apparatus for transmitting data with reduced coupling noise'20097,626,248'Semiconductor package with a controlled impedance bus'20097,536,494'Expandable slave device system with buffered subsystems'20097,222,209'Expandable slave device system'20077,134,101'Active impedance compensation'20067,130,944'Chip-to-chip communication system using an ac-coupled bus and devices employed in same'20067,099,424'Clock data recovery with selectable phase control'2006RE039153'Connector with integral transmission line bus'20066,999,332'Semiconductor package with a controlled impedance bus and method of forming same'20066,968,024'Apparatus and method for operating a master-slave system with a clock signal and a separate phase signal'20056,882,315'Object location system and method'20056,854,030'Integrated circuit device having a capacitive coupling element'20056,731,545'Method and apparatus for reducing worst case power'20046,714,431'Semiconductor package with a controlled impedance bus and method of forming same'20046,687,319'Spread spectrum clocking of digital signals'20046,687,780'Expandable slave device system'20046,657,871'Multiple channel modules and bus systems using same'20036,657,468'Apparatus and method for controlling edge rates of digital signals'20036,621,373'Apparatus and method for utilizing a lossy dielectric substrate in a high speed digital system'20036,621,155'Integrated circuit device having stacked dies and impedance balanced transmission lines'20036,619,973'Chip socket assembly and chip file assembly for semiconductor chips'20036,589,059'Chip socket assembly and chip file assembly for semiconductor chips'20036,583,035'Semiconductor package with a controlled impedance bus and method of forming same'20036,545,875'Multiple channel modules and bus systems using same'20036,530,062'Active impedance compensation'20036,514,794'Redistributed bond pads in stacked integrated circuit die package'20036,504,875'Apparatus for multilevel signaling'20036,496,889'Chip-to-chip communication system using an ac-coupled bus and devices employed in same'20026,447,321'Socket for coupling an integrated circuit package to a printed circuit board'20026,426,984'Apparatus and method for reducing clock signal phase skew in a master-slave system with multiple latent clock cycles'20026,404,660'Semiconductor package with a controlled impedance bus and method of forming same'20026,376,904'Redistributed bond pads in stacked integrated circuit die package'20026,359,931'Apparatus and method for multilevel signaling'20026,352,435'Chip socket assembly and chip file assembly for semiconductor chips'20026,304,104'Method and apparatus for reducing worst case power'20016,287,132'Connector with staggered contact design'20016,273,759'Multi-slot connector with integrated bus providing contact between adjacent modules'20016,266,730'High-frequency bus system'20016,234,820'Method and apparatus for joining printed circuit boards'20016,160,716'Motherboard having one-between trace connections for connectors'20006,067,594'High frequency bus system'20006,007,357'Chip socket assembly and chip file assembly for semiconductor chips'19996,005,895'Apparatus and method for multilevel signaling'19996,002,589'Integrated circuit package for coupling to a printed circuit board'19995,995,016'Method and apparatus for N choose M device selection'19995,908,333'Connector with integral transmission line bus'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2012Patents assigned to RAMBUS INC (49)· patent assignee history
1999–2012Based in Los Altos, CA, US· patent location history
2002–2009Based in North Potomac, MD, US· patent location history
2011–2012Patents assigned to PERINO DONALD V (3)· patent assignee history
2011Patents assigned to GAMINI NADER (1)· patent assignee history
2012Patents assigned to DILLON JOHN B (1)· patent assignee history
2012Patents assigned to KHALILI SAYEH (1)· patent assignee history
2012Based in North Potomoc, MD, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| RAMBUS INC | 49 | 1999–2012 |
| PERINO DONALD Vself | 3 | 2011–2012 |
| DILLON JOHN B | 1 | 2012 |
| GAMINI NADER | 1 | 2011 |
| KHALILI SAYEH | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Altos, California, US | 40 | 1999–2012 |
| North Potomac, Maryland, US | 9 | 2002–2009 |
| North Potomoc, Maryland, US | 1 | 2012 |