Inventor
Nadia M. Rahhal-Orabi
Inventor
Hillsboro, OR, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices27%
H01LSemiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
G06FElectric digital data processing4%
H01GCapacitors4%
H04MTelephonic communication4%
H10BElectronic memory devices4%
B82YSpecific uses or applications of nanostructures2%
PatentTitleYear
10,797,150Differential work function between gate stack metals to reduce parasitic capacitance202010,629,483Self-aligned contacts202010,580,865Transistor with a sub-fin dielectric region under a gate202010,461,082Well-based integration of heteroepitaxial N-type transistors with P-type transistors201910,431,690High electron mobility transistors with localized sub-fin isolation201910,141,226Self-aligned contacts20189,935,205Internal spacers for nanowire transistors and method of fabrication thereof20189,929,273'Apparatus and methods of forming fin structures with asymmetric profile'20189,916,988'Sacrificial material for stripping masking layers'20189,892,967'Self-aligned contacts'20189,508,796'Internal spacers for nanowire transistors and method of fabrication thereof'20169,508,821'Self-aligned contacts'20169,305,771'Prevention of metal loss in wafer processing'20169,224,794'Embedded memory device having MIM capacitor formed in excavated structure'20159,142,421'Double patterning lithography techniques'20159,093,513'Self-aligned contacts'20158,441,057'Embedded memory device having MIM capacitor formed in excavated structure'20138,436,404'Self-aligned contacts'20138,168,488'Systems and methods for reducing contact to gate shorts'20127,968,395'Systems and methods for reducing contact to gate shorts'20117,927,959'Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby'20117,709,866'Method for forming semiconductor contacts'20107,655,986'Systems and methods for reducing contact to gate shorts'20107,314,836'Enhanced nitride layers for metal oxide semiconductors'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2020Patents assigned to INTEL CORP (24)· patent assignee history
2008–2018Based in Hillsboro, OR, US· patent location history
2013–2015Patents assigned to RAHHAL-ORABI NADIA M (3)· patent assignee history
2013–2015Patents assigned to BOHR MARK T (2)· patent assignee history
2013–2015Patents assigned to GHANI TAHIR (2)· patent assignee history
2013–2015Patents assigned to HWANG JACK (2)· patent assignee history
2018–2020Based in Lake Oswego, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 24 | 2008–2020 |
| RAHHAL-ORABI NADIA Mself | 3 | 2013–2015 |
| BOHR MARK T | 2 | 2013–2015 |
| GHANI TAHIR | 2 | 2013–2015 |
| HWANG JACK | 2 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 16 | 2008–2018 |
| Lake Oswego, OR, US | 8 | 2018–2020 |