Inventor
Rajesh S. Parthasarathy
Inventor
Hillsboro, OR, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing85%
G11CStatic stores9%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%
PatentTitleYear
10,678,712Method and apparatus for bus lock assistance202010,409,612Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution201910,409,611Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution201910,216,650Method and apparatus for bus lock assistance201910,175,990Gathering and scattering multiple data elements201910,169,268Providing state storage in a processor for system management mode201910,114,651Gathering and scattering multiple data elements20189,880,948'Method and apparatus for bus lock assistance'20189,535,744'Method and apparatus for continued retirement during commit of a speculative region of code'20179,465,647'Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAM'20169,043,521'Technique for communicating interrupts in a computer system'20158,838,935'Apparatus, method, and system for implementing micro page tables'20148,700,943'Controlling time stamp counter (TSC) offsets for mulitple cores and threads'20148,578,138'Enabling storage of active state in internal storage of processor rather than in SMRAM upon entry to system management mode'20138,447,962'Gathering and scattering multiple data elements'20138,423,682'Address space emulation'20138,312,452'Method and apparatus for a guest to access a privileged register'20128,312,198'Technique for communicating interrupts in a computer system'20128,103,816'Technique for communicating interrupts in a computer system'20127,769,938'Processor selection for an interrupt identifying a processor cluster'20107,627,706'Creation of logical APIC ID with cluster ID and intra-cluster ID'20097,523,152'Methods for supporting extended precision integer divide macroinstructions in a processor'20097,506,121'Method and apparatus for a guest to access a memory mapped device'20097,305,592'Support for nested fault in a virtual machine environment'20077,185,181'Apparatus and method for maintaining a floating point data segment selector'20077,100,029'Performing repeat string operations'20066,944,745'Exception handling for single instructions with multiple data'20056,934,828'Decoupling floating point linear address'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2020Patents assigned to INTEL CORP (28)· patent assignee history
2005–2020Based in Hillsboro, OR, US· patent location history
2012–2018Patents assigned to PARTHASARATHY RAJESH S (5)· patent assignee history
2012–2014Patents assigned to PARTHASARATHY RAJESH (4)· patent assignee history
2012–2018Patents assigned to BRANDT JASON W (3)· patent assignee history
2013–2018Patents assigned to DIXON MARTIN G (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 28 | 2005–2020 |
| PARTHASARATHY RAJESH Sself | 5 | 2012–2018 |
| PARTHASARATHY RAJESHself | 4 | 2012–2014 |
| BRANDT JASON W | 3 | 2012–2018 |
| DIXON MARTIN G | 3 | 2013–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 28 | 2005–2020 |