Inventor
Yong-Jin Yoon
Inventor
Seoul, KR
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores41%
H03KPulse technique25%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses13%
G06FElectric digital data processing6%
C09KMaterials for miscellaneous applications, not provided for elsewhere3%
G01RMeasuring electric variables3%
H01MProcesses or means, e.g. batteries, for the direct conversion of chemical energy into electrical energy3%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution3%
Y02PClimate change mitigation technologies in the production or processing of goods3%
PatentTitleYear
10,637,088Energy conversion device and method of forming the same20208,885,394'Semiconductor device with complementary global bit lines, operating method, and memory system'20148,643,420'Integrated circuit pulse generators'20148,578,227'Delay test device and system-on-chip having the same'20137,586,775'Nonvolatile memory device and related method of operation'20097,400,177'Amplifier circuit having constant output swing range and stable delay time'20087,295,489'Method and circuit for writing double data rate (DDR) sampled data in a memory device'20077,187,214'Amplifier circuit having constant output swing range and stable delay time'20077,154,312'Apparatus for generating internal clock signal'20067,016,257'Semiconductor memory device capable of generating variable clock signals according to modes of operation'20066,992,514'Synchronous mirror delay circuit and semiconductor integrated circuit device having the same'20066,933,758'Synchronous mirror delay circuit with adjustable locking range'20056,661,272'Digitally controllable internal clock generating circuit of semiconductor memory device and method for same'20036,617,894'Circuits and methods for generating internal clock signal of intermediate phase relative to external clock'20036,507,224'High speed input receiver for generating pulse signal'20036,115,298'Semiconductor device with automatic impedance adjustment circuit'20006,114,885'Integrated driver circuits having independently programmable pull-up and pull-down circuits therein which match load impedance'20005,894,233'Sense amplifiers including bipolar transistor input buffers and field effect transistor latch circuits'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2014Patents assigned to SAMSUNG ELECTRONICS CO LTD (16)· patent assignee history
1999–2014Based in Seoul, KR· patent location history
2009Based in Gangseo-gu, KR· patent location history
2013–2014Patents assigned to YOON YONG-JIN (2)· patent assignee history
2013Patents assigned to CHO UK-RAE (1)· patent assignee history
2014Patents assigned to KANG BYUNG-HO (1)· patent assignee history
2014Patents assigned to KIM JI-KYUM (1)· patent assignee history
2020Based in Singapore, SG· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 16 | 1999–2014 |
| YOON YONG-JINself | 2 | 2013–2014 |
| CHO UK-RAE | 1 | 2013 |
| KANG BYUNG-HO | 1 | 2014 |
| KIM JI-KYUM | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Seoul, KR | 16 | 1999–2014 |
| Singapore, SG | 1 | 2020 |
| Gangseo-gu, KR | 1 | 2009 |