Inventor
Tung-Liang Shao
Inventor
Hsinchu, TW
Overview
Patents· 52 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1037%
H01LSemiconductor devices31%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10DInorganic electric semiconductor devices6%
G02BOptical elements, systems or apparatus2%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein2%
H05KPrinted circuits2%
B23KSoldering or unsoldering2%
B29CShaping or joining of plastics2%
F21VFunctional features or details of lighting devices or systems thereof1%
PatentTitleYear
11,107,747Semiconductor package with composite thermal interface material structure and method of forming the same202111,101,195Package structure and method for forming the same202111,056,459Chip package structure and method for forming the same202110,985,121Bump structure and fabricating method thereof202110,879,198Package with solder regions aligned to recesses202010,854,564Semiconductor device and manufacturing method thereof202010,854,580Semiconductor structure along with multiple chips bonded through microbump and manufacturing method thereof202010,825,804Hollow metal pillar packaging scheme202010,734,348Bonded semiconductor devices and methods of forming the same202010,468,385Semiconductor structure including plurality of chips along with air gap and manufacturing method thereof201910,354,986Hollow metal pillar packaging scheme201910,262,958Package with solder regions aligned to recesses201910,229,901Immersion interconnections for semiconductor devices and methods of manufacture thereof201910,163,828Semiconductor device and fabricating method thereof201810,153,218Semiconductor structure and manufacturing method thereof201810,141,291Semiconductor device and method of manufacturing the same201810,068,868Multi-strike process for bonding packages and the packages thereof201810,032,737Semiconductor device and manufacturing method thereof20189,997,467Semiconductor packages and methods of forming the same20189,947,630Package with solder regions aligned to recesses20189,893,046'Thinning process using metal-assisted chemical etching'20189,812,434'Hollow metal pillar packaging scheme'20179,786,591'Capacitor in post-passivation structures and methods of forming the same'20179,679,883'Hollow metal pillar packaging scheme'20179,673,270'Metal insulator metal capacitor and method for making the same'20179,576,929'Multi-strike process for bonding'20179,559,044'Package with solder regions aligned to recesses'20179,530,715'Thermally enhanced structure for multi-chip device'20169,490,203'Capacitor in post-passivation structures and methods of forming the same'20169,484,318'Semiconductor device and manufacturing method thereof'20169,449,927'Seal ring structure with metal-insulator-metal capacitor'20169,355,954'Capacitor in post-passivation structures and methods of forming the same'20169,343,417'Hollow metal pillar packaging scheme'20169,318,456'Self-alignment structure for wafer level chip scale package'20169,153,504'Metal insulator metal capacitor and method for making the same'20159,136,143'Thermally enhanced structure for multi-chip device'20159,136,318'Capacitor in post-passivation structures and methods of forming the same'20159,048,149'Self-alignment structure for wafer level chip scale package'20158,963,328'Reducing delamination between an underfill and a buffer layer in a bond structure'20158,884,400'Capacitor in Post-Passivation structures and methods of forming the same'20148,754,514'Multi-chip wafer level package'20148,685,798'Methods for forming through vias'20148,618,827'Measurement of electrical and mechanical characteristics of low-K dielectric in a semiconductor device'20138,610,267'Reducing delamination between an underfill and a buffer layer in a bond structure'20138,531,032'Thermally enhanced structure for multi-chip device'20138,476,770'Apparatus and methods for forming through vias'20138,227,822'Light emitting diode apparatus'20127,911,556'Backlight module having replaceable lamp module'20117,821,595'Backlight module'20107,782,418'Backlight module'20107,581,866'Replaceable lamp module for liquid crystal display'20096,387,795'Wafer-level packaging'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002Based in Taoyuan, TW· patent location history
2009–2012Patents assigned to AU OPTRONICS CORP (5)· patent assignee history
2009–2021Based in Hsinchu, TW· patent location history
2013–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (13)· patent assignee history
2013–2014Patents assigned to SHAO TUNG-LIANG (5)· patent assignee history
2013–2014Patents assigned to YU CHEN-HUA (4)· patent assignee history
2015–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (33)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 33 | 2015–2021 |
| TAIWAN SEMICONDUCTOR MFG | 13 | 2013–2016 |
| AU OPTRONICS CORP | 5 | 2009–2012 |
| SHAO TUNG-LIANGself | 5 | 2013–2014 |
| YU CHEN-HUA | 4 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 51 | 2009–2021 |
| Taoyuan, TW | 1 | 2002 |