LexDanaLexDanabeta
Inventor

Sung-Taeg Kang

Inventor
Austin, TX, US

Overview

81→
Patents
2004–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 81 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices39%
H10BElectronic memory devices24%
H01LSemiconductor devices15%
B82YSpecific uses or applications of nanostructures8%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
G11CStatic stores6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
10,872,898Embedded non-volatile memory device and fabrication method of the same202010,497,710Split-gate flash cell formed on recessed substrate201910,242,996Method of forming high-voltage transistor with thin gate poly201910,153,349Methods and structures for a split gate memory cell structure20189,853,039Split-gate flash cell formed on recessed substrate20179,818,755'Split-gate flash cell formed on recessed substrate'20179,685,339'Scalable split gate memory cell array'20179,590,058'Methods and structures for a split gate memory cell structure'20179,397,201'Non-volatile memory (NVM) cell and a method of making'20169,368,499'Method of forming different voltage devices with high-k metal gate'20169,356,106'Method to form self-aligned high density nanocrystals'20169,331,092'Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays'20169,318,568'Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor'20169,275,864'Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates'20169,252,246'Integrated split gate non-volatile memory cell and logic device'20169,219,167'Non-volatile memory (NVM) cell'20159,165,652'Split-gate memory cells having select-gate sidewall metal silicide regions and related manufacturing methods'20159,142,566'Method of forming different voltage devices with high-K metal gate'20159,129,855'Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology'20159,112,047'Split gate non-volatile memory (NVM) cell and method therefor'20159,082,650'Integrated split gate non-volatile memory cell and logic structure'20159,054,208'Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays'20159,018,694'Methods and systems for gate dimension control in multi-gate structures for semiconductor devices'20159,006,093'Non-volatile memory (NVM) and high voltage transistor integration'20158,969,940'Method of gate strapping in split-gate memory cell with inlaid gate'20158,962,416'Split gate non-volatile memory cell'20158,953,378'Split gate programming'20158,901,632'Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology'20148,884,358'Method of making a non-volatile memory (NVM) cell structure'20148,877,585'Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration'20148,853,027'Split gate flash cell'20148,778,742'Methods and systems for gate dimension control in multi-gate structures for semiconductor devices'20148,724,399'Methods and systems for erase biasing of split-gate non-volatile memory cells'20148,679,912'Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor'20148,669,609'Non-volatile memory (NVM) cell for endurance and method of making'20148,530,950'Methods and structures for split gate memory'20138,431,471'Method for integrating a non-volatile memory (NVM)'20138,372,699'Method for forming a split-gate memory cell'20138,329,544'Method for forming a semiconductor device having nanocrystals'20128,329,543'Method for forming a semiconductor device having nanocrystals'20128,263,463'Nonvolatile split gate memory cell having oxide growth'20128,178,406'Split gate device and method for forming'20128,173,505'Method of making a split gate memory cell'20128,163,609'Nanocrystal memory with differential energy bands and method of formation'20128,048,738'Method for forming a split gate device'20118,021,970'Method of annealing a dielectric layer'20117,985,649'Method of making a semiconductor structure useful in making a split gate non-volatile memory cell'20117,957,190'Memory having P-type split gate memory cells and method of operation'20117,939,880'Split gate non-volatile memory cell'20117,932,154'Method of fabricating non-volatile flash memory device having at least two different channel concentrations'20117,902,022'Self-aligned in-laid split gate memory and method of making'20117,871,886'Nanocrystal memory with differential energy bands and method of formation'20117,821,055'Stressed semiconductor device and method for making'20107,811,886'Split-gate thin film storage NVM cell with reduced load-up/trap-up effects'20107,799,634'Method of forming nanocrystals'20107,800,158'Semiconductor device and method of forming the same'20107,602,008'Split gate non-volatile memory devices and methods of forming the same'20097,579,243'Split gate memory cell method'20097,553,725'Nonvolatile memory devices and methods of fabricating the same'20097,521,750'Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same'20097,514,739'Nonvolatile semiconductor device and method of fabricating the same'20097,515,468'Nonvolatile memory device'20097,511,334'Twin-ONO-type SONOS memory'20097,411,243'Nonvolatile semiconductor device and method of fabricating the same'20087,408,230'EEPROM device having first and second doped regions that increase an effective channel length'20087,339,232'Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same'20087,320,913'Methods of forming split-gate non-volatile memory devices'20087,320,920'Non-volatile flash memory device having at least two different channel concentrations and method of fabricating the same'20087,315,057'Split gate non-volatile memory devices and methods of forming same'20087,285,820'Flash memory device using semiconductor fin and method thereof'20077,265,410'Non-volatile memory cell having a silicon-oxide-nitride-oxide-silicon gate structure and fabrication method of such cell'20077,265,411'Non-volatile memory having multiple gate structure'20077,256,449'EEPROM device for increasing a coupling ratio and fabrication method thereof'20077,190,021'Non-volatile memory device having improved programming and erasing characteristics and method of fabricating the same'20077,190,024'Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method'20077,041,557'Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method'20067,042,045'Non-volatile memory cell having a silicon-oxide nitride-oxide-silicon gate structure'20067,005,349'Method of manufacturing twin-ONO-type SONOS memory using reverse self-alignment process'20066,960,527'Method for fabricating non-volatile memory device having sidewall gate structure and SONOS cell structure'20056,844,587'Non-volatile memory device having improved programming and erasing characteristics and method of fabricating the same'20056,794,711'Non-volatile memory device having select transistor structure and SONOS cell structure and method for fabricating the device'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2011Patents assigned to SAMSUNG ELECTRONICS CO LTD (26)· patent assignee history
2004–2011Based in Seoul, KR· patent location history
2009–2016Patents assigned to FREESCALE SEMICONDUCTOR INC (47)· patent assignee history
2009–2018Based in Austin, TX, US· patent location history
2012–2017Patents assigned to KANG SUNG-TAEG (29)· patent assignee history
2012–2017Patents assigned to HONG CHEONG MIN (13)· patent assignee history
2012–2017Patents assigned to YATER JANE A (12)· patent assignee history
2017–2020Based in Palo Alto, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
FREESCALE SEMICONDUCTOR INC472009–2016
KANG SUNG-TAEGself292012–2017
SAMSUNG ELECTRONICS CO LTD262004–2011
HONG CHEONG MIN132012–2017
YATER JANE A122012–2017
Locations
LocationPatentsSpan
Austin, Texas, US502009–2018
Seoul, KR262004–2011
Palo Alto, California, US52017–2020