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Inventor

Yasuhiko Kurosawa

Inventor
Fujisawa, JP

Overview

23→
Patents
1999–2021
Patent span
Physics
Primary field (CPC G)

Patents· 23 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing46%
G11CStatic stores31%
H04LTransmission of digital information, e.g. telegraphic communication9%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use9%
G01RMeasuring electric variables3%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
PatentTitleYear
10,884,706Randomization of data using a plurality of types of pseudorandom number generators202110,878,898Memory system and method of controlling memory system for calculating voltage value for reading data202010,658,058Bit error rate estimation for NAND flash memory202010,643,730Adapting flash memory programming parameters for high endurance and steady performance202010,459,691Randomization of data using a plurality of types of pseudorandom number generators201910,430,101Semiconductor memory device that randomizes data and randomizer thereof201910,366,770Bit error rate estimation for NAND flash memory201910,018,673Semiconductor device and current control method of semiconductor device20189,928,920'Memory controller, storage device, and read retry method'20189,921,772'Semiconductor memory device that randomizes data and randomizer thereof'20189,653,156'Memory controller, nonvolatile semiconductor memory device and memory system'20179,625,986'Semiconductor device and temperature control method of semiconductor device'20179,190,159'Semiconductor memory device'20159,129,711'Semiconductor memory device'20159,081,711'Virtual address cache memory, processor and multiprocessor'20158,949,572'Effective address cache memory, processor and effective address caching method'20158,607,024'Virtual address cache memory, processor and multiprocessor'20137,809,890'Systems and methods for increasing yield of devices having cache memories by inhibiting use of defective cache entries'20107,738,483'Systems and methods for managing communication between master and slave devices'20107,409,475'System and method for a high-speed shift-type buffer'20086,643,792'Integrated circuit device having clock frequency changing function, computer system using the integrated circuit device and clock frequency changing method'20036,418,515'Cache flush unit'20025,881,264'Memory controller and memory control system'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2017Patents assigned to TOSHIBA KK (13)· patent assignee history
1999–2002Based in Tokyo, JP· patent location history
2008Based in Austin, TX, US· patent location history
2010–2020Based in Kanagawa, JP· patent location history
2013–2015Patents assigned to HAYASHI HIROO (2)· patent assignee history
2013–2015Patents assigned to IWASA SHIGEAKI (2)· patent assignee history
2013–2015Patents assigned to KUROSAWA YASUHIKO (2)· patent assignee history
2015–2021Based in Fujisawa, JP· patent location history
2018–2021Patents assigned to TOSHIBA MEMORY CORP (10)· patent assignee history
2020Based in Irvine, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TOSHIBA KK131999–2017
TOSHIBA MEMORY CORP102018–2021
HAYASHI HIROO22013–2015
IWASA SHIGEAKI22013–2015
KUROSAWA YASUHIKOself22013–2015
Locations
LocationPatentsSpan
Fujisawa, JP112015–2021
Kanagawa, JP72010–2020
Tokyo, JP21999–2002
Irvine, California, US12020
Austin, Texas, US12008