Inventor

Roy E. Scheuerlein

Inventor

Cupertino, CA, US

Overview

1982–2017

Patent span

Electricity

Primary field (CPC H)

Patents· 271 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores39%

H10BElectronic memory devices20%

H10DInorganic electric semiconductor devices10%

H10NElectric solid-state devices not otherwise provided for9%

B82YSpecific uses or applications of nanostructures5%

H01LSemiconductor devices4%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%

G06FElectric digital data processing2%

PatentTitleYear

RE046435'Three dimensional hexagonal matrix memory array'2017 9,646,688'Three dimensional non-volatile storage with connected word lines'2017 9,576,660'Low forming voltage non-volatile storage device'2017 9,472,301'Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same'2016 9,368,207'Method of operating FET low current 3D re-ram'2016 9,269,425'Low forming voltage non-volatile storage device'2016 9,245,629'Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines'2016 9,202,539'Methods and apparatus for reducing programming time of a memory cell'2015 9,171,584'Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines'2015 9,152,562'Storage sub-system for a computer comprising write-once memory devices and write-many memory devices and related method'2015 9,123,392'Non-volatile 3D memory with cell-selectable word line decoding'2015 9,111,800'Floating body memory cell system and method of manufacture'2015 9,105,576'Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same'2015 9,076,518'Three-dimensional memory structures having shared pillar memory cells'2015 9,065,044'Three dimensional non-volatile storage with connected word lines'2015 9,059,401'Three dimensional non-volatile storage with three device driver for row select'2015 9,047,983'Temperature compensation of conductive bridge memory arrays'2015 9,048,422'Three dimensional non-volatile storage with asymmetrical vertical select devices'2015 9,030,859'Three dimensional non-volatile storage with dual layers of select devices'2015 9,006,795'Resistance-switching memory cells adapted for use at low voltage'2015 8,995,169'Method of operating FET low current 3D Re-RAM'2015 8,969,923'Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning'2015 8,946,017'Method of making a TFT charge storage memory cell having high-mobility corrugated channel'2015 8,934,292'Balanced method for programming multi-layer cell memories'2015 8,923,050'3D memory with vertical bit lines and staircase word lines and vertical switches and methods thereof'2014 8,908,444'Erase for 3D non-volatile memory with sequential selection of word lines'2014 8,885,389'Continuous mesh three dimensional non-volatile storage with vertical select devices'2014 8,883,569'Continuous mesh three dimensional non-volatile storage with vertical select devices'2014 8,885,381'Three dimensional non-volatile storage with dual gated vertical select devices'2014 8,861,258'Set/reset algorithm which detects and repairs weak cells in resistive-switching memory device'2014 8,861,280'Erase for 3D non-volatile memory with sequential selection of word lines'2014 8,848,430'Step soft program for reversible resistivity-switching elements'2014 8,847,200'Memory cell comprising a carbon nanotube fabric element and a steering element'2014 8,848,415'Three dimensional non-volatile storage with multi block row selection'2014 8,841,648'Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same'2014 8,809,128'Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning'2014 8,773,898'Methods and apparatus for reducing programming time of a memory cell'2014 8,766,332'Optimization of critical dimensions and pitch of patterned features in and above a substrate'2014 8,755,223'Three dimensional non-volatile storage with asymmetrical vertical select devices'2014 8,750,066'Temperature compensation of conductive bridge memory arrays'2014 8,741,696'Methods of forming pillars for memory cells using sequential sidewall patterning'2014 8,699,293'Non-volatile storage system with dual block programming'2014 8,693,233'Re-writable resistance-switching memory with balanced series stack'2014 8,686,476'Resistance-switching memory cells adapted for use at low voltage'2014 8,679,967'Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning'2014 8,659,028'Three-dimensional memory device incorporating segmented array line memory array'2014 8,659,932'Single device driver circuit to control three-dimensional memory element array'2014 8,649,206'Multi-bit resistance-switching memory cell'2014 8,637,870'Three-dimensional memory device incorporating segmented array line memory array'2014 8,633,528'Methods and apparatus for increasing memory density using diode layer sharing'2014 8,618,614'Continuous mesh three dimensional non-volatile storage with vertical select devices'2013 8,619,453'Three dimensional non-volatile storage with dual gate selection of vertical bit lines'2013 8,605,486'Cross point non-volatile memory cell'2013 8,575,715'Punch-through diode steering element'2013 8,576,609'Structure and method for biasing phase change memory array for reliable writing'2013 8,576,651'Temperature compensation of conductive bridge memory arrays'2013 8,565,015'Methods of programming two terminal memory cells'2013 8,553,476'Three dimensional memory system with page of data across word lines'2013 8,547,720'Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines'2013 8,547,725'Method of programming a nonvolatile memory cell by reverse biasing a diode steering element to set a storage element'2013 8,536,015'Memory cell that includes a carbon-based memory element and methods of forming the same'2013 8,531,904'Methods and apparatus for extending the effective thermal operating range of a memory'2013 8,509,025'Memory array circuit incorporating multiple array block selection and related method'2013 8,498,146'Programming reversible resistance switching elements'2013 8,482,960'Multi-bit resistance-switching memory cell'2013 8,466,068'Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography'2013 8,462,580'Memory system with reversible resistivity-switching using pulses of alternatrie polarity'2013 8,441,849'Reducing programming time of a memory cell'2013 8,385,141'Structure and method for biasing phase change memory array for reliable writing'2013 8,379,437'Flexible multi-pulse set operation for phase-change memories'2013 8,355,271'Memory system with reversible resistivity-switching using pulses of alternate polarity'2013 8,350,299'Memory with high dielectric constant antifuses adapted for use at low voltage'2013 8,320,196'Semiconductor memory with improved block switching'2012 8,314,023'Methods involving memory with high dielectric constant antifuses adapted for use at low voltage'2012 8,309,415'Methods and apparatus for increasing memory density using diode layer sharing'2012 8,310,892'Capacitive discharge method for writing to non-volatile memory'2012 8,289,749'Soft forming reversible resistivity-switching element for bipolar switching'2012 8,283,706'Optimization of critical dimensions and pitch of patterned features in and above a substrate'2012 8,284,589'Single device driver circuit to control three-dimensional memory element array'2012 8,279,704'Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same'2012 8,274,130'Punch-through diode steering element'2012 8,275,927'Storage sub-system for a computer comprising write-once memory devices and write-many memory devices and related method'2012 8,270,199'Cross point non-volatile memory cell'2012 8,270,210'Pulse reset for non-volatile storage'2012 8,270,202'Programming non-volatile storage element using current from other element'2012 8,203,864'Memory cell and methods of forming a memory cell comprising a carbon nanotube fabric element and a steering element'2012 8,154,904'Programming reversible resistance switching elements'2012 8,149,607'Rewritable memory device with multi-level, write-once memory cells'2012 8,139,391'Multi-bit resistance-switching memory cell'2012 8,138,010'Method for fabricating high density pillar structures by double patterning using positive photoresist'2012 8,125,822'Reducing programming time of a memory cell'2012 8,120,068'Three-dimensional memory structures having shared pillar memory cells'2012 8,110,863'TFT charge storage memory cell having high-mobility corrugated channel'2012 8,110,476'Memory cell that includes a carbon-based memory element and methods of forming the same'2012 8,107,270'Three dimensional hexagonal matrix memory array'2012 8,105,867'Self-aligned three-dimensional non-volatile memory fabrication'2012 8,102,698'Structure and method for biasing phase change memory array for reliable writing'2012 8,098,511'Reverse set with current limit for non-volatile storage'2012 8,094,510'Memory array incorporating noise detection line'2012 8,059,447'Capacitive discharge method for writing to non-volatile memory'2011 8,050,109'Semiconductor memory with improved memory block switching'2011 8,040,721'Creating short program pulses in asymmetric memory arrays'2011 8,014,185'Multiple series passive element matrix cell for three-dimensional arrays'2011 8,004,927'Reversible-polarity decoder circuit and method'2011 8,004,919'Methods and apparatus for extending the effective thermal operating range of a memory'2011 7,982,209'Memory cell comprising a carbon nanotube fabric element and a steering element'2011 7,978,498'Programming non-volatile storage element using current from other element'2011 7,978,507'Pulse reset for non-volatile storage'2011 7,961,494'Non-volatile multi-level re-writable memory cell incorporating a diode in series with multiple resistors and method for writing same'2011 7,943,515'Shared masks for x-lines and shared masks for y-lines for fabrication of 3D memory arrays'2011 7,944,728'Programming a memory cell with a diode in series by applying reverse bias'2011 7,940,554'Reduced complexity array line drivers for 3D matrix arrays'2011 7,935,553'Method for fabricating high density pillar structures by double patterning using positive photoresist'2011 7,923,812'Quad memory cell and method of making same'2011 7,924,602'Method to program a memory cell comprising a carbon nanotube fabric element and a steering element'2011 7,910,407'Quad memory cell and method of making same'2011 7,887,999'Method of making a pillar pattern using triple or quadruple exposure'2011 7,869,258'Reverse set with current limit for non-volatile storage'2011 7,859,884'Structure and method for biasing phase change memory array for reliable writing'2010 7,851,851'Three dimensional NAND memory'2010 7,848,145'Three dimensional NAND memory'2010 7,829,875'Nonvolatile rewritable memory cell comprising a resistivity-switching oxide or nitride and an antifuse'2010 7,830,722'Floating body memory cell system and method of manufacture'2010 7,812,335'Sidewall structured switchable resistor cell'2010 7,808,038'Method of making three dimensional NAND memory'2010 7,800,933'Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance'2010 7,781,269'Triangle two dimensional complementary patterning of pillars'2010 7,773,446'Methods and apparatus for extending the effective thermal operating range of a memory'2010 7,773,443'Current sensing method and apparatus for a memory array'2010 7,764,534'Two terminal nonvolatile memory using gate controlled diode elements'2010 7,764,549'Floating body memory cell system and method of manufacture'2010 7,746,680'Three dimensional hexagonal matrix memory array'2010 7,745,265'Method of making three dimensional NAND memory'2010 7,732,235'Method for fabricating high density pillar structures by double patterning using positive photoresist'2010 7,733,685'Cross point memory cell with distributed diodes and method of making same'2010 7,719,874'Systems for controlled pulse operations in non-volatile memory'2010 7,697,366'Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers'2010 7,696,812'Cooperative charge pump circuit and method'2010 7,667,999'Method to program a memory cell comprising a carbon nanotube fabric and a steering element'2010 7,656,734'Methods and apparatus for extending the effective thermal operating range of a memory'2010 7,633,828'Hierarchical bit line bias bus for block selectable memory array'2009 7,596,050'Method for using a hierarchical bit line bias bus for block selectable memory array'2009 7,575,973'Method of making three dimensional NAND memory'2009 7,570,523'Method for using two data busses for memory array block selection'2009 7,554,832'Passive element memory array incorporating reversible polarity word line and bit line decoders'2009 7,542,337'Apparatus for reading a multi-level passive element memory cell array'2009 7,542,370'Reversible polarity decoder circuit'2009 7,542,338'Method for reading a multi-level passive element memory cell array'2009 7,525,869'Method for using a reversible polarity decoder circuit'2009 7,522,448'Controlled pulse operations in non-volatile memory'2009 7,514,321'Method of making three dimensional NAND memory'2009 7,508,714'Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block'2009 7,505,344'Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics'2009 7,505,321'Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same'2009 7,499,304'Systems for high bandwidth one time field-programmable memory'2009 7,499,366'Method for using dual data-dependent busses for coupling read/write circuits to a memory array'2009 7,499,355'High bandwidth one time field-programmable memory'2009 7,495,500'Method for using a multiple polarity reversible charge pump circuit'2009 7,495,947'Reverse bias trim operations in non-volatile memory'2009 7,492,630'Systems for reverse bias trim operations in non-volatile memory'2009 7,486,587'Dual data-dependent busses for coupling read/write circuits to a memory array'2009 7,486,537'Method for using a mixed-use memory array with different data states'2009 7,477,093'Multiple polarity reversible charge pump circuit'2009 7,474,000'High density contact to relaxed geometry layers'2009 7,465,951'Write-once nonvolatile phase change memory array'2008 7,463,536'Memory array incorporating two data busses for memory array block selection'2008 7,463,546'Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders'2008 7,450,414'Method for using a mixed-use memory array'2008 7,447,056'Method for using a multi-use memory cell and memory array'2008 7,433,233'NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same'2008 7,426,128'Switchable resistive memory with opposite polarity write pulses'2008 7,423,304'Optimization of critical dimensions and pitch of patterned features in and above a substrate'2008 7,383,476'System architecture and method for three-dimensional memory'2008 7,362,604'Apparatus and method for programming an array of nonvolatile memory cells including switchable resistor memory elements'2008 7,359,279'Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers'2008 7,351,992'Forming nonvolatile phase change memory cell having a reduced thermal contact area'2008 7,345,907'Apparatus and method for reading an array of nonvolatile memory cells including switchable resistor memory elements'2008 7,317,641'Volatile memory cell two-pass writing method'2008 7,307,268'Structure and method for biasing phase change memory array for reliable writing'2007 7,298,665'Dual-mode decoder circuit, integrated circuit memory array incorporating same, and related methods of operation'2007 7,280,397'Three-dimensional non-volatile SRAM incorporating thin-film device layer'2007 7,272,052'Decoding circuit for non-binary groups of memory line drivers'2007 7,259,038'Forming nonvolatile phase change memory cell having a reduced thermal contact area'2007 7,243,203'Pipeline circuit for low latency memory'2007 7,233,024'Three-dimensional memory device incorporating segmented bit line memory array'2007 7,233,522'NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same'2007 7,221,588'Memory array incorporating memory cells arranged in NAND strings'2007 7,218,570'Apparatus and method for memory operations using address-dependent conditions'2007 7,219,271'Memory device and method for redundancy/self-repair'2007 7,177,183'Multiple twin cell non-volatile memory array and logic block structure and method therefor'2007 7,177,181'Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics'2007 7,177,169'Word line arrangement having multi-layer word line segments for three-dimensional memory array'2007 7,177,191'Integrated circuit including memory array incorporating multiple types of NAND string structures'2007 7,177,227'Transistor layout configuration for tight-pitched memory array lines'2007 7,142,471'Method and apparatus for incorporating block redundancy in a memory array'2006 7,132,335'Semiconductor device with localized charge storage dielectric and method of making same'2006 7,106,652'Word line arrangement having multi-layer word line segments for three-dimensional memory array'2006 7,054,219'Transistor layout configuration for tight-pitched memory array lines'2006 7,023,739'NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same'2006 7,022,572'Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells'2006 7,023,260'Charge pump circuit incorporating corresponding parallel charge pump stages and method therefor'2006 7,005,350'Method for fabricating programmable memory array structures incorporating series-connected transistor strings'2006 7,002,825'Word line arrangement having segmented word lines'2006 6,996,017'Redundant memory structure using bad bit pointers'2006 6,989,575'Formation of arrays of microelectronic elements'2006 6,975,555'Magnetic random access memory using memory cells with rotated magnetic storage elements'2005 6,965,527'Multibank memory on a die'2005 6,963,504'Apparatus and method for disturb-free programming of passive element memory cells'2005 6,960,794'Formation of thin channels for TFT devices to ensure low variability of threshold voltages'2005 6,954,394'Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions'2005 6,940,109'High density 3d rail stack arrays and method of making'2005 6,937,495'Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics'2005 6,928,590'Memory device and method for storing bits in non-adjacent storage locations in a memory array'2005 6,895,490'Method for making a write-once memory device read compatible with a write-many file system'2005 6,894,936'Memory device and method for selectable sub-array activation'2005 6,889,307'Integrated circuit incorporating dual organization memory array'2005 6,879,505'Word line arrangement having multi-layer word line segments for three-dimensional memory array'2005 6,868,022'Redundant memory structure using bad bit pointers'2005 6,859,410'Tree decoder structure particularly well-suited to interfacing array lines having extremely small layout pitch'2005 6,856,572'Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device'2005 6,849,905'Semiconductor device with localized charge storage dielectric and method of making same'2005 6,822,903'Apparatus and method for disturb-free programming of passive element memory cells'2004 6,816,431'Magnetic random access memory using memory cells with rotated magnetic storage elements'2004 6,816,410'Method for programming a three-dimensional memory array incorporating serial chain diode stack'2004 6,807,119'Array containing charge storage and dummy transistors and method of operating the array'2004 6,781,878'Dynamic sub-array group selection scheme'2004 6,778,431'Architecture for high-speed magnetic memories'2004 6,768,685'Integrated circuit memory array with fast test mode utilizing multiple word line selection and method therefor'2004 6,765,813'Integrated systems using vertically-stacked three-dimensional memory cells'2004 6,754,102'Method for programming a three-dimensional memory array incorporating serial chain diode stack'2004 6,737,675'High density 3D rail stack arrays'2004 6,735,546'Memory device and method for temperature-based control over write and/or read operations'2004 6,735,104'Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays'2004 6,724,665'Memory device and method for selectable sub-array activation'2004 6,711,043'Three-dimensional memory cache system'2004 6,661,730'Partial selection of passive element memory cell sub-arrays for write operation'2003 6,633,509'Partial selection of passive element memory cell sub-arrays for write operations'2003 6,631,085'Three-dimensional memory array incorporating serial chain diode stack'2003 6,618,295'Method and apparatus for biasing selected and unselected array lines when writing a memory array'2003 6,574,145'Memory device and method for sensing while programming a non-volatile memory cell'2003 6,567,287'Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays'2003 6,562,634'Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method of forming the same'2003 6,545,898'Method and apparatus for writing memory arrays using external source of high programming voltage'2003 6,522,594'Memory array incorporating noise detection line'2003 6,515,897'Magnetic random access memory using a non-linear memory element select mechanism'2003 6,515,904'Method and system for increasing programming bandwidth in a non-volatile memory device'2003 6,504,753'Method and apparatus for discharging memory array lines'2003 6,430,660'Unified memory hard disk drive system'2002 6,404,671'Data-dependent field compensation for writing magnetic random access memories'2002 6,391,658'Formation of arrays of microelectronic elements'2002 6,351,023'Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same'2002 6,335,890'Segmented write line architecture for writing magnetic random access memories'2002 6,331,944'Magnetic random access memory using a series tunnel element select mechanism'2001 6,269,018'Magnetic random access memory using current through MTJ write mechanism'2001 6,269,040'Interconnection network for connecting memory cells to sense amplifiers'2001 6,242,770'Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method for forming the same'2001 6,191,989'Current sensing amplifier'2001 6,180,444'Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same'2001 6,130,835'Voltage biasing for magnetic RAM with magnetic tunnel memory cells'2000 6,097,625'Magnetic random access memory (MRAM) array with magnetic tunnel junction (MTJ) cells and remote diodes'2000 6,005,800'Magnetic memory array with paired asymmetric memory cells for improved write margin'1999 5,991,193'Voltage biasing for magnetic ram with magnetic tunnel memory cells'1999 5,793,697'Read circuit for magnetic memory array using magnetic tunnel junction devices'1998 5,640,343'Magnetic memory array using magnetic tunnel junction devices in the memory cells'1997 4,675,982'Method of making self-aligned recessed oxide isolation regions'1987 4,651,183'High density one device memory cell arrays'1987 RE032236'One device field effect transistor (FET) AC stable random access memory (RAM) array'1986 4,574,365'Shared access lines memory cells'1986 4,527,254'Dynamic random access memory having separated V.sub.DD pads for improved burn-in'1985 4,506,351'One-device random access memory having enhanced sense signal'1985 4,319,342'One device field effect transistor (FET) AC stable random access memory (RAM) array'1982

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1982–2006Patents assigned to IBM (27)· patent assignee history

1982Based in Wappingers Falls, NY, US· patent location history

1985–1987Based in Burlington, VT, US· patent location history

1986–1987Based in Sunnyvale, CA, US· patent location history

1997–2017Based in Cupertino, CA, US· patent location history

2003–2006Patents assigned to MATRIX SEMICONDUCTOR INC (45)· patent assignee history

2006–2017Patents assigned to SANDISK 3D LLC (189)· patent assignee history

2011–2015Patents assigned to SCHEUERLEIN ROY E (63)· patent assignee history

2012–2015Patents assigned to SCHEUERLEIN ROY (8)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SANDISK 3D LLC	189	2006–2017
SCHEUERLEIN ROY Eself	63	2011–2015
MATRIX SEMICONDUCTOR INC	45	2003–2006
IBM	27	1982–2006
SCHEUERLEIN ROYself	8	2012–2015

Locations

Location	Patents	Span
Cupertino, California, US	264	1997–2017
Burlington, VT, US	4	1985–1987
Sunnyvale, California, US	2	1986–1987
Wappingers Falls, New York, US	1	1982