Inventor

Shigekazu Yamada

Inventor
Tokyo, JP

Overview

77→
Patents
1997–2020
Patent span
Physics
Primary field (CPC G)

Patents· 77 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores95%
G01RMeasuring electric variables3%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems1%
LOC131%
PatentTitleYear
10,803,957Monitoring and charging inhibit bit-line202010,796,778Apparatuses and methods to control body potential in 3D non-volatile memory operations202010,741,263Standby biasing techniques to reduce read disturbs202010,706,912Memories configured to control discharge of a control gate voltage of a transistor connected between a data line and a common source202010,591,541Comparator202010,586,600High-voltage shifter with reduced transistor degradation202010,510,397Integrated circuit devices configured to control discharge of a control gate voltage201910,510,419Monitoring and charging inhibit bit-line201910,490,292Apparatuses and methods to control body potential in 3D non-volatile memory operations201910,446,236Memory device and method of operation201910,347,320Controlling discharge of a control gate voltage201910,170,196Apparatuses and methods to control body potential in 3D non-volatile memory operations201910,056,149Semiconductor memory column decoder device and method20189,881,686'Apparatuses and methods to control body potential in 3D non-volatile memory operations'20189,704,542'Automatic word line leakage measurement circuitry'20179,697,912'Leakage current detection'20179,536,618'Apparatuses and methods to control body potential in memory operations'20179,466,380'Semiconductor memory column decoder device and method'20169,443,610'Leakage current detection'20169,424,936'Current leakage reduction in 3D NAND memory'20169,312,018'Sensing with boost'20169,269,410'Leakage measurement systems'20169,183,948'Apparatuses, integrated circuits, and methods for measuring leakage current'20159,159,452'Automatic word line leakage measurement circuitry'20159,064,577'Apparatuses and methods to control body potential in memory operations'20158,947,946'Leakage measurement systems'20158,873,297'Select gate programming in a memory device'20148,867,290'Apparatuses, integrated circuits, and methods for measuring leakage current'20148,760,933'Circuits, systems, and methods for driving high and low voltages on bit lines in non-volatile memory'20148,634,264'Apparatuses, integrated circuits, and methods for measuring leakage current'20148,588,007'Leakage measurement systems'20138,542,534'Select gate programming in a memory device'20138,503,249'Semiconductor memory column decoder device and method'20138,482,986'Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same'20138,462,559'Memory erase methods and devices'20138,363,490'Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory'20138,284,613'Semiconductor memory device having bit line pre-charge unit separated from data register'20128,238,165'Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same'20128,194,446'Methods for programming a memory device and memory devices using inhibit voltages that are less than a supply voltage'20128,089,816'Memory erase methods and devices'20128,045,395'Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory'20118,000,151'Semiconductor memory column decoder device and method'20117,920,428'Methods and apparatuses relating to automatic cell threshold voltage measurement'20117,916,518'VCC control inside data register of memory device'20117,916,546'Methods for programming a memory device and memory devices using inhibit voltages that are less than a supply voltage'20117,872,920'Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same'20117,800,953'Method and system for selectively limiting peak power consumption during programming or erase of non-volatile memory devices'20107,768,817'VCC control inside data register of memory device'20107,746,701'Semiconductor memory device having bit line pre-charge unit separated from data register'20107,719,899'Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory'20107,609,559'Word line drivers having a low pass filter circuit in non-volatile memory device'20097,567,462'Method and system for selectively limiting peak power consumption during programming or erase of non-volatile memory devices'20097,483,305'Method, apparatus and system relating to automatic cell threshold voltage measurement'20097,450,460'Voltage control circuit and semiconductor device'20087,280,413'Nonvolatile semiconductor memory'20077,227,778'Semiconductor device and writing method'20077,206,232'Semiconductor device and source voltage control method'20077,184,338'Semiconductor device, semiconductor device testing method, and programming method'20077,158,417'Semiconductor device and method for writing data into the semiconductor device'20077,082,066'Flash memory having spare sector with shortened access time'20066,944,057'Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference'20056,912,160'Nonvolatile semiconductor memory device'20056,859,393'Ground structure for page read and page write for flash memory'20056,839,279'Nonvolatile semiconductor memory device'20056,816,423'System for control of pre-charge levels in a memory device'20046,781,884'System for setting memory voltage threshold'20046,621,742'System for programming a flash memory device'20036,594,181'System for reading a double-bit memory cell'20036,542,409'System for reference current tracking in a semiconductor device'20036,438,041'Negative voltage regulation'20026,400,638'Wordline driver for flash memory read mode'20026,324,108'Application of external voltage during array VT testing'20016,208,564'High voltage comparator'20016,147,906'Method and system for saving overhead program time in a memory device'2000D0400182'Motor controller'19985,708,602'Non-volatile semiconductor memory device and method for verifying operating of the same'19985,615,154'Flash memory device having erase verification'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2007Patents assigned to FUJITSU LTD (15)· patent assignee history
1997–2007Based in Kawasaki, JP· patent location history
2000–2002Patents assigned to ADVANCED MICRO DEVICES INC (4)· patent assignee history
2000–2005Based in Cupertino, CA, US· patent location history
2006–2008Patents assigned to SPANSION LLC (6)· patent assignee history
2006–2020Based in Suginami-ku, JP· patent location history
2007–2020Based in Tokyo, JP· patent location history
2009–2020Patents assigned to MICRON TECHNOLOGY INC (49)· patent assignee history
2009Based in Tokoyo, JP· patent location history
2012–2015Patents assigned to YAMADA SHIGEKAZU (13)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC492009–2020
FUJITSU LTD151997–2007
YAMADA SHIGEKAZUself132012–2015
SPANSION LLC62006–2008
ADVANCED MICRO DEVICES INC42000–2002
Locations
LocationPatentsSpan
Tokyo, JP452007–2020
Suginami-ku, JP132006–2020
Cupertino, California, US112000–2005
Kawasaki, JP51997–2007
Tokoyo, JP12009