Inventor
Shawn Searles
Inventor
Austin, TX, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices12%
G06FElectric digital data processing10%
H10DInorganic electric semiconductor devices10%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses7%
G11CStatic stores6%
H03KPulse technique6%
H01GCapacitors4%
H10BElectronic memory devices4%
PatentTitleYear
11,063,046Multi-die fine grain integrated voltage regulation202110,868,243Co-fired passive integrated circuit devices202010,818,632Structure and method for fabricating a computing system with an integrated voltage regulator module202010,601,330Tertiary winding for coupled inductor structures202010,587,195Integrated passive devices to reduce power supply voltage droop202010,520,970Multi-phase current mode control loop incorporating a distributed transconductance stage201910,491,120Constant off-time control method for buck converters using coupled inductors201910,431,737Co-fired passive integrated circuit devices201910,411,012Multi-die fine grain integrated voltage regulation201910,122,275Constant off-time control method for buck converters using coupled inductors201810,122,269Current mode control of a buck converter using coupled inductance201810,062,838Co-fired passive integrated circuit devices201810,056,384Multi-die fine grain integrated voltage regulation20189,935,076Structure and method for fabricating a computing system with an integrated voltage regulator module20189,595,526'Multi-die fine grain integrated voltage regulation'20179,548,288'Integrated circuit die decoupling system with reduced inductance'20179,397,567'Shunt integrated voltage regulator'20169,306,457'Instantaneous load current monitoring'20169,274,938'Dynamic RAM Phy interface with configurable power states'20168,937,499'Method for locking a delay locked loop'20158,729,944'Clock generator with integrated phase offset programmability'20148,719,598'Power OK distribution for multi-voltage chips'20148,638,145'Method for locking a delay locked loop'20148,607,104'Memory diagnostics system and method with hardware-based read/write patterns'20138,542,068'Oscillator with highly-adjustable bang-bang control'20138,356,155'Dynamic RAM Phy interface with configurable power states'20137,983,362'Programmable data sampling receiver for digital data signals'20117,961,533'Method and apparatus for implementing write levelization in memory subsystems'20117,929,361'Circuit using a shared delay locked loop (DLL) and method therefor'20117,924,637'Method for training dynamic random access memory (DRAM) controller timing delays'20117,872,937'Data driver circuit for a dynamic random access memory (DRAM) controller or the like and method therefor'20117,869,287'Circuit for locking a delay locked loop (DLL) and method therefor'20117,826,279'Programmable bias circuit architecture for a digital data/clock receiver'20107,770,037'Power ok distribution for multi-voltage chips'20107,770,049'Controller for clock skew determination and reduction based on a lead count over multiple clock cycles'20107,765,425'Incrementally adjustable skew and duty cycle correction for clock signals within a clock distribution network'20107,701,263'Cascode driver with gate oxide protection'20107,652,937'Programmable linear receiver for digital data clock signals'20107,652,524'Voltage source for gate oxide protection'20107,561,625'Method and apparatus for crosstalk reduction'20097,345,992'System and method for embedding a sub-channel in a block coded data stream'20087,260,155'Method and apparatus for encoding and decoding digital communications data'20077,158,575'System and method for embedding a sub-channel in a block coded data stream'20076,111,898'Method of establishing when to propagate the output of a multiplexer'20005,179,303'Signal delay apparatus employing a phase locked loop'19935,146,121'Signal delay apparatus employing a phase locked loop'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–1993Based in Ottawa, CA· patent location history
2000–2008Based in Beaverton, OR, US· patent location history
2009–2016Patents assigned to ADVANCED MICRO DEVICES INC (18)· patent assignee history
2009–2021Based in Austin, TX, US· patent location history
2010–2011Patents assigned to GLOBALFOUNDRIES INC (4)· patent assignee history
2013–2014Patents assigned to SEARLES SHAWN (6)· patent assignee history
2016–2021Patents assigned to APPLE INC (16)· patent assignee history
2018–2020Patents assigned to APPLE (3)· patent assignee history
2018–2020Based in Cupertino, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 18 | 2009–2016 |
| APPLE INC | 16 | 2016–2021 |
| SEARLES SHAWNself | 6 | 2013–2014 |
| GLOBALFOUNDRIES INC | 4 | 2010–2011 |
| APPLE | 3 | 2018–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 37 | 2009–2021 |
| Beaverton, OR, US | 4 | 2000–2008 |
| Cupertino, California, US | 3 | 2018–2020 |
| Ottawa, CA | 2 | 1992–1993 |