Inventor
Nicolas L. Breil
Inventor
Wappingers Falls, NY, US
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices28%
H10DInorganic electric semiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10BElectronic memory devices5%
C07FAcyclic, carbocyclic or heterocyclic compounds containing elements other than carbon, hydrogen, halogen, oxygen, nitrogen, sulfur, selenium or tellurium2%
C23CCoating metallic material2%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
G01QScanning-probe techniques or apparatus1%
G05BControl or regulating systems in general1%
PatentTitleYear
11,088,280Transistor and method of forming same202111,069,809Soi FinFET fins with recessed fins and epitaxy in source drain region202110,950,450Silicide films through selective deposition202110,922,809Method for detecting voids and an inspection system202110,707,167Contacts to semiconductor substrate and methods of forming same202010,607,841Silicide films through selective deposition202010,096,609Modified tungsten silicon201810,068,920Silicon germanium fins on insulator formed by lateral recrystallization20189,997,407Voidless contact metal structures20189,911,849'Transistor and method of forming same'20189,905,692'SOI FinFET fins with recessed fins and epitaxy in source drain region'20189,865,546'Contacts to semiconductor substrate and methods of forming same'20189,859,403'Multiple step thin film deposition method for high conformality'20189,859,216'Voidless contact metal structures'20189,653,535'DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods'20179,595,524'FinFET source-drain merged by silicide-based material'20179,543,167'FinFET source-drain merged by silicide-based material'20179,496,329'DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods'20169,472,406'Metal semiconductor alloy contact resistance improvement'20169,449,921'Voidless contact metal structures'20169,449,827'Metal semiconductor alloy contact resistance improvement'20169,443,772'Diffusion-controlled semiconductor contact creation'20169,431,534'Asymmetric field effect transistor cap layer'20169,379,012'Oxide mediated epitaxial nickel disilicide alloy contact formation'20169,379,207'Stable nickel silicide formation with fluorine incorporation and related IC structure'20169,373,512'Apparatus and method for laser heating and ion implantation'20169,335,759'Optimization of a laser anneal beam path for maximizing chip yield'20169,318,336'Non-volatile memory structure employing high-k gate dielectric and metal gate'20169,299,766'DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods'20169,293,554'Self-aligned liner formed on metal semiconductor alloy contacts'20169,236,345'Oxide mediated epitaxial nickel disilicide alloy contact formation'20169,166,014'Gate electrode with stabilized metal semiconductor alloy-semiconductor stack'20159,099,394'Non-volatile memory structure employing high-k gate dielectric and metal gate'20159,093,424'Dual silicide integration with laser annealing'20159,093,425'Self-aligned liner formed on metal semiconductor alloy contacts'20159,034,749'Gate electrode with stabilized metal semiconductor alloy-semiconductor stack'20158,603,887'Method for depositing a silicon oxide layer of same thickness on silicon and on silicon-germanium'20138,552,369'Obtaining elemental concentration profile of sample'2013Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2013–2021Patents assigned to IBM (18)· patent assignee history
2013–2016Patents assigned to BREIL NICOLAS (3)· patent assignee history
2013Patents assigned to ST MICROELECTRONICS CROLLES 2 (2)· patent assignee history
2013–2017Based in Wappingers Falls, NY, US· patent location history
2015–2020Patents assigned to GLOBALFOUNDRIES INC (17)· patent assignee history
2015–2016Based in Grenoble, FR· patent location history
2016–2021Based in Beacon, NY, US· patent location history
2018–2021Based in San Jose, CA, US· patent location history
2018–2021Based in Mountain View, CA, US· patent location history
2020–2021Patents assigned to APPLIED MATERIALS INC (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 18 | 2013–2021 |
| GLOBALFOUNDRIES INC | 17 | 2015–2020 |
| APPLIED MATERIALS INC | 3 | 2020–2021 |
| BREIL NICOLASself | 3 | 2013–2016 |
| ST MICROELECTRONICS CROLLES 2 | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Wappingers Falls, New York, US | 15 | 2013–2017 |
| Beacon, New York, US | 9 | 2016–2021 |
| San Jose, California, US | 4 | 2018–2021 |
| Grenoble, FR | 4 | 2015–2016 |
| Mountain View, California, US | 3 | 2018–2021 |