Inventor
John C. Holst
Inventor
San Jose, CA, US
Overview
Patents· 37 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores24%
H03KPulse technique13%
H10DInorganic electric semiconductor devices13%
G06FElectric digital data processing12%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
H04LTransmission of digital information, e.g. telegraphic communication3%
H10BElectronic memory devices3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
PatentTitleYear
9,583,180'Low-power row-oriented memory write assist circuit'20178,547,155'Soft error robust low power latch device layout techniques'20138,270,399'Crossbar apparatus for a forwarding table memory in a router'20127,600,181'Circuit to reduce rail noise voltage spikes due to switching on an input-output bus'20097,450,438'Crossbar apparatus for a forwarding table memory in a router'20087,026,691'Minimizing transistor size in integrated circuits'20066,420,767'Capacitively coupled DTMOS on SOI'20026,376,880'High-speed lateral bipolar device in SOI process'20026,287,953'Minimizing transistor size in integrated circuits'20016,258,642'Use of functional memory cells as guard cells in a semiconductor memory'20016,213,869'MOSFET-type device with higher driver current and lower steady state power dissipation'20016,191,034'Forming minimal size spaces in integrated circuit conductive lines'20016,188,596'Layout for semiconductor memory including multi-level sensing'20016,157,244'Power supply independent temperature sensor'20006,157,584'Redundancy circuit and method for semiconductor memory'20006,153,912'SOI with conductive metal substrate used as VSS connection'20006,146,954'Minimizing transistor size in integrated circuits'20006,127,880'Active power supply filter'20006,111,794'Memory interface circuit including bypass data forwarding with essentially no delay'20006,084,454'Start-up circuit for write selects and equilibrates'20006,058,447'Handshake circuit and operating method for self-resetting circuits'20006,054,918'Self-timed differential comparator'20006,051,881'Forming local interconnects in integrated circuits'20006,046,088'Method for self-aligning polysilicon gates with field isolation and the resultant structure'20005,999,039'Active power supply filter'19995,964,884'Self-timed pulse control circuit'19995,959,467'High speed dynamic differential logic circuit employing capacitance matching devices'19995,940,334'Memory interface circuit including bypass data forwarding with essentially no delay'19995,930,659'Forming minimal size spaces in integrated circuit conductive lines'19995,920,515'Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device'19995,883,826'Memory block select using multiple word lines to address a single memory cell row'19995,844,836'Memory cell having increased capacitance via a local interconnect to gate capacitor and a method for making such a cell'19985,796,651'Memory device using a reduced word line voltage during read operations and a method of accessing such a memory device'19985,790,461'Register file with bypass capability'19985,598,115'Comparator cell for use in a content addressable memory'19975,446,685'Pulsed ground circuit for CAM and PAL memories'19955,299,147'Decoder scheme for fully associative translation-lookaside buffer'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–1998Patents assigned to INTERGRAPH CORP (4)· patent assignee history
1994–2012Based in San Jose, CA, US· patent location history
1998–2006Patents assigned to ADVANCED MICRO DEVICES INC (26)· patent assignee history
1999Patents assigned to ADVANCED MICRODEVICES INC (1)· patent assignee history
2008–2017Patents assigned to CISCO TECH INC (5)· patent assignee history
2012–2013Patents assigned to HOLST JOHN C (2)· patent assignee history
2013–2017Based in Saratoga, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 26 | 1998–2006 |
| CISCO TECH INC | 5 | 2008–2017 |
| INTERGRAPH CORP | 4 | 1994–1998 |
| HOLST JOHN Cself | 2 | 2012–2013 |
| ADVANCED MICRODEVICES INC | 1 | 1999 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 35 | 1994–2012 |
| Saratoga, California, US | 2 | 2013–2017 |