Inventor
HE-ZHOU WAN
Inventor
CN
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores71%
H03KPulse technique16%
H10BElectronic memory devices5%
H01LSemiconductor devices4%
G06FElectric digital data processing2%
H10DInorganic electric semiconductor devices2%
PatentTitleYear
12,537,037Integrated circuit with asymmetric arrangements of memory arrays202612,518,809Memory device with write circuit and method of operating the same202612,512,136Integrated circuit with asymmetric arrangements of memory arrays202512,469,531Signal generator for controlling timing of signal in memory device202512,412,625Static random access memory with adaptive precharge signal generated in response to tracking operation202512,211,586Signal generator for controlling timing of signal in memory device202512,198,754Timing control circuit of memory device with tracking word line and tracking bit line202512,193,206Memory device202512,190,940Memory device and operating method thereof202512,190,984Circuit and method of operating the same202512,183,428Memory circuit and method of operating the same202412,184,285Latch circuit and memory device202412,183,432Shared decoder circuit and method202412,176,062Memory device202412,080,372System and method of power management in memory design202412,002,542Write circuit of memory device and method of operating the same202412,002,507Static random access memory with adaptive precharge signal generated in response to tracking operation202411,923,041Signal generator for controlling timing of signal in memory device202411,862,231Memory device and operating method thereof202411,811,404Latch circuit, memory device and method202311,769,539Integrated circuit with asymmetric arrangements of memory arrays202311,735,251Timing control circuit of memory device with tracking word line and tracking bit line202311,721,374Control circuit of memory device202311,715,505Memory circuit and method of operating the same202311,705,175Shared decoder circuit and method202311,705,174Integrated circuit with asymmetric arrangements of memory arrays202311,651,134Method of certifying safety levels of semiconductor memories in integrated circuits202311,557,336Static random access memory with adaptive precharge signal generated in response to tracking operation202311,545,192System and method of power management in memory design202311,545,191Circuit and method of operating the same202311,521,662Write circuit of memory device202211,514,974Memory device202211,468,929Memory circuit and method of operating the same202211,462,551Memory device202211,450,367Shared decoder circuit and method202211,398,261Method and signal generator for controlling timing of signal in memory device202211,393,509Control circuit of memory device202211,289,141Integrated circuit with asymmetric arrangements of memory arrays202211,190,169Latch circuit, memory device and method2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (39)· patent assignee history
2021–2026Patents assigned to TSMC CHINA COMPANY LTD (39)· patent assignee history
2021Patents assigned to TSMC CHINA COMPANY LIMIIED (1)· patent assignee history
2021–2026Based in CN· patent location history
2022–2025Patents assigned to TSMC NANJING COMPANY LTD (18)· patent assignee history
2022–2025Based in TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 39 | 2021–2026 |
| TSMC CHINA COMPANY LTD | 39 | 2021–2026 |
| TSMC NANJING COMPANY LTD | 18 | 2022–2025 |
| TSMC CHINA COMPANY LIMIIED | 1 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| CN | 26 | 2021–2026 |
| TW | 13 | 2022–2025 |