Inventor
Philip Raymond Germann
Inventor
Oronoco, MN, US
Overview
Patents· 86 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing29%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H05KPrinted circuits9%
G11CStatic stores8%
G01RMeasuring electric variables6%
H10DInorganic electric semiconductor devices5%
Y10TTechnical subjects covered by former us classification5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
B23KSoldering or unsoldering3%
PatentTitleYear
9,739,825'Residual material detection in backdrilled stubs'20179,612,988'Donor cores to improve integrated circuit yield'20179,488,690'Residual material detection in backdrilled stubs'20169,341,670'Residual material detection in backdrilled stubs'20169,312,199'Intelligent chip placement within a three-dimensional chip stack'20169,281,261'Intelligent chip placement within a three-dimensional chip stack'20169,207,275'Interconnect solder bumps for die testing'20159,003,559'Continuity check monitoring for microchip exploitation detection'20158,823,090'Field-effect transistor and method of creating same'20148,796,578'Implementing selective rework for chip stacks and silicon carrier assemblies'20148,788,748'Implementing memory interface with configurable bandwidth'20148,642,456'Implementing semiconductor signal-capable capacitors with deep trench and TSV technologies'20148,639,879'Sorting movable memory hierarchies in a computer system'20148,519,304'Implementing selective rework for chip stacks and silicon carrier assemblies'20138,492,903'Through silicon via direct FET signal gating'20138,491,739'Implementing interleaved-dielectric joining of multi-layer laminates'20138,466,024'Power domain controller with gated through silicon via having FET with horizontal channel'20138,332,659'Signal quality monitoring to defeat microchip exploitation'20128,255,628'Structure for multi-level memory architecture with data prioritization'20128,214,657'Resistance sensing for defeating microchip exploitation'20128,172,140'Doped implant monitoring for microchip tamper detection'20128,174,103'Enhanced architectural interconnect options enabled with flipped die on a multi-chip package'20128,108,647'Digital data architecture employing redundant links in a daisy chain of component modules'20128,079,134'Method of enhancing on-chip inductance structure utilizing silicon through via technology'20118,037,270'Structure for memory chip for high capacity memory subsystem supporting replication of command data'20118,037,272'Structure for memory chip for high capacity memory subsystem supporting multiple speed bus'20118,037,258'Structure for dual-mode memory chip for high capacity memory subsystem'20118,019,949'High capacity memory subsystem architecture storing interleaved data for reduced bus speed'20117,996,641'Structure for hub for supporting high capacity memory subsystem'20117,954,081'Implementing enhanced wiring capability for electronic laminate packages'20117,952,478'Capacitance-based microchip exploitation detection'20117,945,883'Apparatus, and computer program for implementing vertically coupled noise control through a mesh plane in an electronic package design'20117,921,264'Dual-mode memory chip for high capacity memory subsystem'20117,921,271'Hub for supporting high capacity memory subsystem'20117,884,625'Capacitance structures for defeating microchip tampering'20117,882,479'Method and apparatus for implementing redundant memory access using multiple controllers on the same bank of memory'20117,852,103'Implementing at-speed Wafer Final Test (WFT) with complete chip coverage'20107,844,769'Computer system having an apportionable data bus and daisy chained memory chips'20107,838,336'Method and structure for dispensing chip underfill through an opening in the chip'20107,822,936'Memory chip for high capacity memory subsystem supporting replication of command data'20107,818,512'High capacity memory subsystem architecture employing hierarchical tree configuration of memory modules'20107,809,913'Memory chip for high capacity memory subsystem supporting multiple speed bus'20107,810,065'System and method for implementing optimized creation of openings for de-gassing in an electronic package'20107,791,978'Design structure of implementing power savings during addressing of DRAM architectures'20107,725,762'Implementing redundant memory access using multiple controllers on the same bank of memory'20107,707,379'Dynamic latency map for memory optimization'20107,701,244'False connection for defeating microchip exploitation'20107,675,164'Method and structure for connecting, stacking, and cooling chips on a flexible carrier'20107,673,093'Computer system having daisy chained memory chips'20107,667,487'Techniques for providing switchable decoupling capacitors for an integrated circuit'20107,660,942'Daisy chainable self timed memory chip'20107,660,940'Carrier having daisy chain of self timed memory chips'20107,650,455'Spider web interconnect topology utilizing multiple port connection'20107,627,711'Memory controller for daisy chained memory chips'20097,620,763'Memory chip having an apportionable data bus'20097,617,350'Carrier having daisy chained memory chips'20097,577,811'Memory controller for daisy chained self timed memory chips'20097,553,696'Method for implementing component placement suspended within grid array packages for enhanced electrical performance'20097,546,410'Self timed memory chip having an apportionable data bus'20097,545,664'Memory system having self timed daisy chained memory chips'20097,496,711'Multi-level memory architecture with data prioritization'20097,492,662'Structure and method of implementing power savings during addressing of DRAM architectures'20097,490,186'Memory system having an apportionable data bus and daisy chained memory chips'20097,480,201'Daisy chainable memory chip'20097,477,568'Using common mode differential data signals of DDR2 SDRAM for control signal transmission'20097,472,360'Method for implementing enhanced wiring capability for electronic laminate packages'20087,472,368'Method for implementing vertically coupled noise control through a mesh plane in an electronic package design'20087,402,912'Method and power control structure for managing plurality of voltage islands'20087,362,651'Using common mode differential data signals of DDR2 SDRAM for control signal transmission'20087,345,901'Computer system having daisy chained self timed memory chips'20087,345,900'Daisy chained memory system'20087,342,816'Daisy chainable memory chip'20087,326,857'Method and structure for creating printed circuit boards with stepped thickness'20087,317,401'Method and mechanical tamper-evident case fastener'20087,202,685'Embedded probe-enabling socket with integral probe structures'20077,088,200'Method and structure to control common mode impedance in fan-out regions'20067,088,199'Method and stiffener-embedded waveguide structure for implementing enhanced data transfer'20067,074,050'Socket assembly with incorporated memory structure'20067,050,871'Method and apparatus for implementing silicon wafer chip carrier passive devices'20067,036,710'Method and structures for implementing impedance-controlled coupled noise suppressor for differential interface solder column array'20067,036,709'Method and structure for implementing column attach coupled noise suppressor'20066,998,852'Method and apparatus for implementing direct attenuation measurement through embedded structure excitation'20066,987,397'Method and probe structure for implementing a single probe location for multiple signals'20066,956,383'Method and apparatus for implementing automated electronic package transmission line characteristic impedance verification'20056,842,038'Self optimizing off chip driver'20056,757,175'Method and embedded bus bar structure for implementing power distribution'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2017Patents assigned to IBM (86)· patent assignee history
2004–2006Based in Rochester, MN, US· patent location history
2006–2017Based in Oronoco, MN, US· patent location history
2012–2015Patents assigned to GERMANN PHILIP R (12)· patent assignee history
2012–2015Patents assigned to BARTLEY GERALD K (11)· patent assignee history
2012–2015Patents assigned to BECKER DARRYL J (6)· patent assignee history
2012–2015Patents assigned to MAKI ANDREW B (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 86 | 2004–2017 |
| GERMANN PHILIP Rself | 12 | 2012–2015 |
| BARTLEY GERALD K | 11 | 2012–2015 |
| BECKER DARRYL J | 6 | 2012–2015 |
| MAKI ANDREW B | 6 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Oronoco, Minnesota, US | 82 | 2006–2017 |
| Rochester, Minnesota, US | 4 | 2004–2006 |