Inventor
Lloyd G. Burrell
Inventor
Poughkeepsie, NY, US
Overview
Patents· 9 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1075%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
PatentTitleYear
7,867,820'Methods for forming co-planar wafer-scale chip packages'20117,405,108'Methods for forming co-planar wafer-scale chip packages'20087,294,565'Method of fabricating a wire bond pad with Ni/Au metallization'20077,250,311'Wirebond crack sensor for low-k die'20077,087,997'Copper to aluminum interlayer interconnect using stud and via liner'20067,037,824'Copper to aluminum interlayer interconnect using stud and via liner'20066,960,831'Semiconductor device having a composite layer in addition to a barrier layer between copper wiring and aluminum bond pad'20056,908,841'Support structures for wirebond regions of contact pads over low modulus materials'20056,559,042'Process for forming fusible links'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2011Patents assigned to IBM (9)· patent assignee history
2003–2011Based in Poughkeepsie, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 9 | 2003–2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 9 | 2003–2011 |