Inventor
Markus Kuhn
Inventor
Hillsboro, OR, US
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices36%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H01LSemiconductor devices13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
A61BDiagnosis4%
H10NElectric solid-state devices not otherwise provided for4%
A61LMethods or apparatus for sterilising materials or objects in general2%
B05DProcesses for applying fluent materials to surfaces, in general2%
B25BTools or bench devices not otherwise provided for, for fastening, connecting, disengaging, or holding2%
B82YSpecific uses or applications of nanostructures2%
PatentTitleYear
10,897,009Resistive memory cells and precursors thereof, methods of making the same, and devices including the same202110,516,109Resistive memory cells and precursors thereof, methods of making the same, and devices including the same201910,463,411Surgical retaining instruments for bone plates201910,400,801Compact unit201910,304,929Two-dimensional condensation for uniaxially strained semiconductor fins20199,711,598'Two-dimensional condensation for uniaxially strained semiconductor fins'20179,680,013'Non-planar device having uniaxially strained semiconductor body and method of making same'20179,419,140'Two-dimensional condensation for uniaxially strained semiconductor fins'20169,159,835'Two-dimensional condensation for uniaxially strained semiconductor fins'20158,992,582'Fixation devices and method'20158,558,279'Non-planar device having uniaxially strained semiconductor body and method of making same'20138,551,555'Biocompatible coatings for medical devices'20138,487,348'Methods and apparatus to reduce layout based strain variations in non-planar transistor structures'20138,299,617'Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects'20128,269,283'Methods and apparatus to reduce layout based strain variations in non-planar transistor structures'20128,211,772'Two-dimensional condensation for uniaxially strained semiconductor fins'20127,727,892'Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects'20107,709,909'Method for making a semiconductor device having a high-k gate dielectric'20107,442,983'Method for making a semiconductor device having a high-k gate dielectric'20087,420,254'Semiconductor device having a metal gate electrode'20087,339,271'Metal-metal oxide etch stop/barrier for integrated circuit interconnects'20087,192,890'Depositing an oxide'20077,122,870'Methods of forming a multilayer stack alloy for work function engineering'20067,084,038'Method for making a semiconductor device having a high-k gate dielectric'20067,074,680'Method for making a semiconductor device having a high-k gate dielectric'20066,890,807'Method for making a semiconductor device having a metal gate electrode'20056,849,509'Methods of forming a multilayer stack alloy for work function engineering'20056,794,755'Surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement'20046,787,440'Method for making a semiconductor device having an ultra-thin high-k gate dielectric'20046,721,423'Lost cost countermeasures against compromising electromagnetic computer emanations'20046,689,675'Method for making a semiconductor device having a high-k gate dielectric'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2021Patents assigned to INTEL CORP (27)· patent assignee history
2004–2021Based in Hillsboro, OR, US· patent location history
2006–2013Based in Portland, OR, US· patent location history
2007–2019Based in Beaverton, OR, US· patent location history
2012–2019Patents assigned to KUHN MARKUS (10)· patent assignee history
2012–2016Patents assigned to CEA STEPHEN M (6)· patent assignee history
2012–2016Patents assigned to KAVALIEROS JACK T (6)· patent assignee history
2012–2013Patents assigned to GILES MARTIN D (3)· patent assignee history
2015–2019Based in Freiburg, DE· patent location history
2019Based in Wadern-Krettnich, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 27 | 2004–2021 |
| KUHN MARKUSself | 10 | 2012–2019 |
| CEA STEPHEN M | 6 | 2012–2016 |
| KAVALIEROS JACK T | 6 | 2012–2016 |
| GILES MARTIN D | 3 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 13 | 2004–2021 |
| Beaverton, OR, US | 9 | 2007–2019 |
| Portland, OR, US | 5 | 2006–2013 |
| Freiburg, DE | 2 | 2015–2019 |
| Wadern-Krettnich, DE | 1 | 2019 |