Inventor
Robert P. Kurshan
Inventor
New York, NY, US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing65%
G01RMeasuring electric variables8%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner5%
H03HImpedance networks, e.g. resonant circuits5%
H03DDemodulation or transference of modulation from one carrier to another3%
H03KPulse technique3%
H04BTransmission3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H04QSelecting3%
H04WWireless communication networks3%
PatentTitleYear
9,047,427'Method and system for performing verification of an electronic design'20158,539,405'Method and system for implementing top down design and verification of an electronic design'20138,234,609'Method and system for implementing top down design and verification of an electronic design'20127,937,673'Method and system for implementing top down design and verification of an electrical circuit design'20117,712,059'Coverage metric and coverage computation for verification based on design partitions'20107,444,274'Method and system for verifying circuit designs through propagation of assertions'20087,181,708'Coverage metric and coverage computation for verification based on design partitions'20077,047,510'Method and system for partitioning an integrated circuit design'20066,708,143'Verification coverage method'20046,591,231'Method for identifying cyclicity in circuit designs'20036,311,293'Detecting of model errors through simplification of model via state reachability analysis'20016,295,515'Static partial order reduction'20016,209,120'Verifying hardware in its software context and vice-versa'20016,185,516'Automata-theoretic verification of systems'20016,102,959'Verification tool computation reduction'20006,099,575'Constraint validity checking'20005,966,516'Apparatus for defining properties in finite-state machines'19995,946,481'Method for detecting errors in models through restriction'19995,926,622'Efficient regression verification'19995,901,073'Method for detecting errors in models through restriction'19995,740,084'Verification of homomorphism between two system models'19985,691,925'Deriving tractable sub-system for model of larger system'19975,483,470'Timing verification by successive approximation'19965,163,016'Analytical development and verification of control-intensive systems'19924,361,875'Multiple tone detector and locator'19824,348,735'Cyclotomic tone detector and locator'19824,333,156'Broadband cyclotomic tone detector'19823,971,998'Recursive detector-oscillator circuit'19763,963,905'Periodic sequence generators using ordinary arithmetic'1976Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1976–1982Patents assigned to BELL TELEPHONE LABOR INC (5)· patent assignee history
1976–2015Based in New York, NY, US· patent location history
1997–2004Patents assigned to LUCENT TECHNOLOGIES INC (13)· patent assignee history
2006–2015Patents assigned to CADENCE DESIGN SYSTEMS INC (8)· patent assignee history
2012–2015Patents assigned to KURSHAN ROBERT P (3)· patent assignee history
2012–2013Patents assigned to MCMILLAN KENNETH L (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LUCENT TECHNOLOGIES INC | 13 | 1997–2004 |
| CADENCE DESIGN SYSTEMS INC | 8 | 2006–2015 |
| BELL TELEPHONE LABOR INC | 5 | 1976–1982 |
| KURSHAN ROBERT Pself | 3 | 2012–2015 |
| MCMILLAN KENNETH L | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| New York, New York, US | 29 | 1976–2015 |