Inventor

Christian Jacobi

Inventor

Poughkeepsie, NY, US

Overview

1999–2021

Patent span

Physics

Primary field (CPC G)

Patents· 333 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing84%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%

H03MCoding3%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

G11CStatic stores1%

H04LTransmission of digital information, e.g. telegraphic communication1%

H03KPulse technique1%

A61PSpecific therapeutic activity of chemical compounds or medicinal preparations1%

G06VImage or video recognition or understanding1%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%

PatentTitleYear

11,108,567Compute digital signature authentication verify instruction2021 11,080,087Transaction begin/end instructions2021 11,080,064Instructions controlling access to shared registers of a multi-threaded processor2021 11,080,052Determining the effectiveness of prefetch instructions2021 11,075,763Compute digital signature authentication sign with encrypted key instruction2021 11,074,203Handling an input/output store instruction2021 11,068,266Handling an input/output store instruction2021 11,068,303Adjusting thread balancing in response to disruptive complex instruction2021 11,061,680Instructions controlling access to shared registers of a multi-threaded processor2021 11,048,475Multi-cycle key compares for keys and records of variable length2021 11,048,635Controlling a rate of prefetching based on bus bandwidth2021 11,010,168Effectiveness and prioritization of prefetches2021 11,010,276Configurable code fingerprint2021 11,010,307Cache management2021 11,010,298Reducing cache transfer overhead in a system2021 11,010,066Identifying processor attributes based on detecting a guarded storage event2021 11,003,452Effectiveness and prioritization of prefetches2021 10,997,079Method and arrangement for saving cache power2021 10,983,833Virtualized and synchronous access to hardware accelerators2021 10,970,224Operational context subspaces2021 10,963,380Cache miss thread balancing2021 10,956,341Multi-engine address translation facility2021 10,956,156Conditional transaction end instruction2021 10,956,168Post completion execution in an out-of-order processor design2021 10,956,337Temporarily suppressing processing of a restrained storage operand request2021 10,949,212Saving and restoring machine state between multiple executions of an instruction2021 10,936,283Buffer size optimization in a hierarchical structure2021 10,929,312Zone-SDID mapping scheme for TLB purges2021 10,929,130Guarded storage event handling during transactional execution2021 10,915,547Optimizing data conversion using pattern frequency2021 10,901,736Conditional instruction end operation2021 10,896,022Sorting using pipelined compare units2021 10,884,754Infinite processor thread balancing2021 10,831,503Saving and restoring machine state between multiple executions of an instruction2020 10,831,478Sort and merge instruction for a general-purpose processor2020 10,831,502Migration of partially completed instructions2020 10,831,664Cache structure using a logical directory2020 10,831,674Translation support for a virtual cache2020 10,831,497Compression/decompression instruction specifying a history buffer to be used in the compression/decompression of data2020 10,831,476Compare and delay instructions2020 10,824,426Generating and verifying hardware instruction traces including memory data contents2020 10,824,508High efficiency redundant array of independent memory2020 10,810,134Sharing virtual and real translations in a virtual cache2020 10,802,986Marking to indicate memory used to back address translation structures2020 10,795,824Speculative data return concurrent to an exclusive invalidate request2020 10,740,240Method and arrangement for saving cache power2020 10,740,248Methods and systems for predicting virtual address2020 10,733,199Optimizing data conversion using pattern frequency2020 10,732,858Loading and storing controls regulating the operation of a guarded storage facility2020 10,725,685Load logical and shift guarded instruction2020 10,725,738Adaptive sort accelerator sharing first level processor cache2020 10,719,415Randomized testing within transactional execution2020 10,719,294Hardware sort accelerator sharing first level processor cache2020 10,713,168Cache structure using a logical directory2020 10,713,048Conditional branch to an indirectly specified location2020 10,698,836Translation support for a virtual cache2020 10,691,412Parallel sort accelerator sharing first level processor cache2020 10,691,604Minimizing cache latencies using set predictors2020 10,684,863Restricted instructions in transactional execution2020 10,684,951Minimizing cache latencies using set predictors2020 10,671,532Reducing cache transfer overhead in a system2020 10,673,460Spilling temporary results for accommodation of memory boundaries2020 10,671,390Conditional instruction end operation2020 10,656,950Spin loop delay instruction2020 10,656,945Next instruction access intent instruction for indicating usage of a storage operand by one or more instructions subsequent to a next sequential instruction2020 10,657,059Controlling a rate of prefetching based on bus bandwidth2020 10,649,778Performance optimized congruence class matching for multiple concurrent radix translations2020 10,635,603Multi-engine address translation facility2020 10,635,592Controlling a rate of prefetching based on bus bandwidth2020 10,621,090Facility for extending exclusive hold of a cache line in private cache2020 10,621,105Multi-engine address translation facility2020 10,606,597Nontransactional store instruction2020 10,606,762Sharing virtual and real translations in a virtual cache2020 10,599,431Managing backend resources via frontend steering or stalls2020 10,599,435Nontransactional store instruction2020 10,592,142Toggling modal transient memory access state2020 10,585,800Reducing cache transfer overhead in a system2020 10,585,797Operating different processor cache levels2020 10,579,514Alignment based block concurrency for accessing memory2020 10,579,332Hardware sort accelerator sharing first level processor cache2020 10,579,377Guarded storage event handling during transactional execution2020 10,579,499Task latency debugging in symmetric multiprocessing computer systems2020 10,579,525Reducing cache transfer overhead in a system2020 10,572,384Operating different processor cache levels2020 10,572,254Instruction to query cache residency2020 10,558,464Infinite processor thread balancing2020 10,558,465Restricted instructions in transactional execution2020 10,558,552Configurable code fingerprint2020 10,528,482Cache management2020 10,528,472Method and arrangement for saving cache power2020 10,521,351Temporarily suppressing processing of a restrained storage operand request2019 10,521,506Memory preserving parse tree based compression with entropy coding2019 10,521,350Determining the effectiveness of prefetch instructions2019 10,514,911Structure for microprocessor including arithmetic logic units and an efficiency logic unit2019 10,503,503Generating design structure for microprocessor with arithmetic logic units and an efficiency logic unit2019 10,496,405Generating and verifying hardware instruction traces including memory data contents2019 10,496,292Saving/restoring guarded storage controls in a virtualized environment2019 10,496,311Run-time instrumentation of guarded storage event processing2019 10,452,395Instruction to query cache residency2019 10,452,288Identifying processor attributes based on detecting a guarded storage event2019 10,445,248Host page management using active guest page table indicators2019 10,437,602Program interruption filtering in transactional execution2019 10,430,195Stream based branch prediction index accelerator with power prediction2019 10,430,246Virtualized and synchronous access to hardware accelerators2019 10,430,199Program interruption filtering in transactional execution2019 10,430,188Next instruction access intent instruction for indicating usage of a storage operand by one or more instructions subsequent to a next sequential instruction2019 10,417,252Optimizing data conversion using pattern frequency2019 10,387,311Cache directory that determines current state of a translation in a microprocessor core cache2019 10,379,862Effectiveness and prioritization of prefeteches2019 10,380,033Multi-engine address translation facility2019 10,380,032Multi-engine address translation facility2019 10,372,457Effectiveness and prioritization of prefetches2019 10,365,929Spin loop delay instruction2019 10,365,928Suppress unnecessary mapping for scratch register2019 10,360,033Conditional transaction end instruction2019 10,353,827Zone-SDID mapping scheme for TLB purges2019 10,353,759Facilitating transaction completion subsequent to repeated aborts of the transaction2019 10,353,828Zone-SDID mapping scheme for TLB purges2019 10,353,817Cache miss thread balancing2019 10,339,049Garbage collection facility grouping infrequently accessed data units in designated transient memory area2019 10,331,446Generating and verifying hardware instruction traces including memory data contents2019 10,324,728Lightweight interrupts for condition checking2019 10,318,790Code fingerprint-based processor malfunction detection2019 10,318,415Garbage collection facility grouping infrequently accessed data units in designated transient memory area2019 10,303,575Time-slice-instrumentation facility2019 10,303,759Memory preserving parse tree based compression with entropy coding2019 10,303,545High efficiency redundant array of independent memory2019 10,296,348Delayed allocation of an out-of-order queue entry and based on determining that the entry is unavailable, enable deadlock avoidance involving reserving one or more entries in the queue, and disabling deadlock avoidance based on expiration of a predetermined amount of time2019 10,282,276Fingerprint-initiated trace extraction2019 10,282,305Selective purging of entries of structures associated with address translation in a virtualized environment2019 10,275,254Spin loop delay instruction2019 10,268,582Operating different processor cache levels2019 10,241,924Reducing over-purging of structures associated with address translation using an array of tags2019 10,235,174Conditional instruction end operation2019 10,229,061Method and arrangement for saving cache power2019 10,223,214Randomized testing within transactional execution2019 10,185,588Transaction begin/end instructions2019 10,176,111Host page management using active guest page table indicators2019 10,168,902Reducing purging of structures associated with address translation2019 10,169,239Managing a prefetch queue based on priority indications of prefetch requests2019 10,169,243Reducing over-purging of structures associated with address translation2019 10,169,038Compare and delay instructions2019 10,157,119Configurable code fingerprint2018 10,120,681Compare and delay instructions2018 10,083,124Translating virtual memory addresses to physical addresses2018 10,068,069Denoting precise locations and arguments in binary program code2018 10,025,589Conditional transaction end instruction2018 9,996,360Transaction abort instruction specifying a reason for abort2018 9,983,882Selectively controlling instruction execution in transactional processing2018 9,983,915Facilitating transaction completion subsequent to repeated aborts of the transaction2018 9,983,883Transaction abort instruction specifying a reason for abort2018 9,983,881Selectively controlling instruction execution in transactional processing2018 9,971,626Coherence protocol augmentation to indicate transaction status2018 9,959,117Instruction to load data up to a specified memory boundary indicated by the instruction2018 9,959,118Instruction to load data up to a dynamically determined memory boundary2018 9,952,862Instruction to load data up to a dynamically determined memory boundary2018 9,946,521Programmable code fingerprint2018 9,946,589Structure for reducing power consumption for memory device2018 9,946,542Instruction to load data up to a specified memory boundary indicated by the instruction2018 9,946,588Structure for reducing power consumption for memory device2018 9,940,264Load and store ordering for a strongly ordered simultaneous multithreading core2018 9,910,769'Alignment based block concurrency for accessing memory'2018 9,904,618'Alignment based block concurrency for accessing memory'2018 9,898,348'Resource mapping in multi-threaded central processor units'2018 9,886,327'Resource mapping in multi-threaded central processor units'2018 9,886,397'Load and store ordering for a strongly ordered simultaneous multithreading core'2018 9,858,082'Restricted instructions in transactional execution'2018 9,851,978Restricted instructions in transactional execution2017 9,836,405Dynamic management of virtual memory blocks exempted from cache memory access2017 9,817,693'Coherence protocol augmentation to indicate transaction status'2017 9,811,337'Transaction abort processing'2017 9,792,125'Saving/restoring selected registers in transactional processing'2017 9,792,124'Speculative branch handling for transaction abort'2017 9,772,854'Selectively controlling instruction execution in transactional processing'2017 9,766,925'Transactional processing'2017 9,760,511'Efficient interruption routing for a multithreaded processor'2017 9,740,521'Constrained transaction execution'2017 9,740,549'Facilitating transaction completion subsequent to repeated aborts of the transaction'2017 9,727,484'Dynamic cache memory management with translation lookaside buffer protection'2017 9,720,764'Uncorrectable memory errors in pipelined CPUs'2017 9,720,441'Generating time-of-day values without causing execution stalls'2017 9,716,515'Method for detecting end of record in variable length coded bit stream'2017 9,715,377'Behavior based code recompilation triggering scheme'2017 9,710,266'Instruction to compute the distance to a specified memory boundary'2017 9,710,267'Instruction to compute the distance to a specified memory boundary'2017 9,703,907'RAS evaluation for circuit element'2017 9,697,132'Store forwarding cache'2017 9,680,653'Cipher message with authentication instruction'2017 9,665,486'Hierarchical cache structure and handling thereof'2017 9,665,376'Sharing program interrupt logic in a multithreaded processor'2017 9,639,370'Software instructed dynamic branch history pattern adjustment'2017 9,626,293'Single-thread cache miss rate estimation'2017 9,619,385'Single thread cache miss rate estimation'2017 9,619,237'Speculative branch handling for transaction abort'2017 9,612,963'Store forwarding cache'2017 9,594,683'Data processing in a multiple processor system to maintain multiple processor cache memory access coherency'2017 9,582,413'Alignment based block concurrency for accessing memory'2017 9,569,370'Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB)'2017 9,569,573'RAS evaluation for circuit element'2017 9,569,338'Fingerprint-initiated trace extraction'2017 9,563,568'Hierarchical cache structure and handling thereof'2017 9,558,032'Conditional instruction end operation'2017 9,552,278'Configurable code fingerprint'2017 9,547,484'Automated compiler operation verification'2017 9,547,523'Conditional instruction end operation'2017 9,529,598'Transaction abort instruction'2016 9,524,205'Code fingerprint-based processor malfunction detection'2016 9,507,602'Sharing program interrupt logic in a multithreaded processor'2016 9,495,225'Parallel execution mechanism and operating method thereof'2016 9,495,157'Fingerprint-based branch prediction'2016 9,495,306'Dynamic management of a processor state with transient cache memory'2016 9,495,138'Scheme for verifying the effects of program optimizations'2016 9,483,409'Store forwarding cache'2016 9,477,514'Transaction begin/end instructions'2016 9,471,504'Store forwarding cache'2016 9,471,312'Instruction to load data up to a dynamically determined memory boundary'2016 9,459,875'Dynamic enablement of multithreading'2016 9,459,868'Instruction to load data up to a dynamically determined memory boundary'2016 9,459,867'Instruction to load data up to a specified memory boundary indicated by the instruction'2016 9,460,023'Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB)'2016 9,454,377'Speculative branch handling for transaction abort'2016 9,454,370'Conditional transaction end instruction'2016 9,455,742'Compression ratio for a compression engine'2016 9,448,796'Restricted instructions in transactional execution'2016 9,448,797'Restricted instructions in transactional execution'2016 9,442,738'Restricting processing within a processor to facilitate transaction completion'2016 9,442,737'Restricting processing within a processor to facilitate transaction completion'2016 9,436,477'Transaction abort instruction'2016 9,430,235'Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors'2016 9,424,012'Programmable code fingerprint'2016 9,424,035'Conditional transaction end instruction'2016 9,419,646'Hardware compression to find backward references with multi-level hashes'2016 9,411,588'Conditional transaction end instruction'2016 9,411,599'Operand fetching control as a function of branch confidence'2016 9,411,664'Fingerprint-based processor parameter management'2016 9,400,752'Store forwarding cache'2016 9,395,998'Selectively controlling instruction execution in transactional processing'2016 9,395,961'Fingerprint-based code version selection'2016 9,396,125'Dynamic management of memory ranges exempted from cache memory access'2016 9,384,004'Randomized testing within transactional execution'2016 9,384,131'Systems and methods for accessing cache memory'2016 9,383,996'Instruction to load data up to a specified memory boundary indicated by the instruction'2016 9,378,024'Randomized testing within transactional execution'2016 9,378,143'Managing transactional and non-transactional store observability'2016 9,367,324'Saving/restoring selected registers in transactional processing'2016 9,367,378'Facilitating transaction completion subsequent to repeated aborts of the transaction'2016 9,367,323'Processor assist facility'2016 9,361,115'Saving/restoring selected registers in transactional processing'2016 9,354,925'Transaction abort processing'2016 9,354,883'Dynamic enablement of multithreading'2016 9,348,642'Transaction begin/end instructions'2016 9,336,046'Transaction abort processing'2016 9,336,007'Processor assist facility'2016 9,323,673'Hierarchical cache structure and handling thereof'2016 9,317,460'Program event recording within a transactional environment'2016 9,311,101'Intra-instructional transaction abort handling'2016 9,311,137'Delaying interrupts for a transactional-execution facility'2016 9,311,259'Program event recording within a transactional environment'2016 9,298,631'Managing transactional and non-transactional store observability'2016 9,292,453'Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB)'2016 9,292,443'Multilevel cache system'2016 9,286,076'Intra-instructional transaction abort handling'2016 9,274,957'Monitoring a value in storage without repeated storage access'2016 9,274,959'Handling virtual memory address synonyms in a multi-level cache hierarchy structure'2016 9,262,320'Tracking transactional execution footprint'2016 9,262,625'Address translation/specification field for hardware accelerator'2016 9,256,729'Address translation/specification field for hardware accelerator'2016 9,250,915'Operand fetching control as a function of branch confidence'2016 9,235,539'Program event recording within a transactional environment'2016 9,223,687'Determining the logical address of a transaction abort'2015 9,223,574'Start virtual execution instruction for dispatching multiple threads in a computer'2015 9,218,288'Monitoring a value in storage without repeated storage access'2015 9,207,706'Generating monotonically increasing TOD values in a multiprocessor system'2015 9,209,831'Hardware compression to find backward references with multi-level hashes'2015 9,197,243'Compression ratio for a compression engine'2015 9,183,146'Hierarchical cache structure and handling thereof'2015 9,164,911'Atomic execution over accesses to multiple memory locations in a multiprocessor system'2015 9,152,566'Prefetch address translation using prefetch buffer based on availability of address translation logic'2015 9,135,005'History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties'2015 9,104,399'Dual issuing of complex instruction set instructions'2015 9,052,889'Load pair disjoint facility and instruction therefor'2015 9,052,945'Transaction begin/end instructions'2015 9,052,946'Constrained transaction execution'2015 9,015,419'Avoiding aborts due to associativity conflicts in a transactional environment'2015 8,977,823'Store buffer for transactional memory'2015 8,966,324'Transactional execution branch indications'2015 8,887,002'Transactional execution branch indications'2014 8,887,003'Transaction diagnostic block'2014 8,880,959'Transaction diagnostic block'2014 8,850,166'Load pair disjoint facility and instruction therefore'2014 8,806,179'Non-quiescing key setting facility'2014 8,799,583'Atomic execution over accesses to multiple memory locations in a multiprocessor system'2014 8,751,775'Non-quiescing key setting facility'2014 8,688,661'Transactional processing'2014 8,682,877'Constrained transaction execution'2014 8,645,669'Cracking destructively overlapping operands in variable length instructions'2014 8,521,992'Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors'2013 8,516,200'Avoiding cross-interrogates in a streaming data optimized L1 cache'2013 8,495,452'Handling corrupted background data in an out of order execution environment'2013 8,495,341'Instruction length based cracking for instruction of variable length storage operands'2013

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2007–2021Patents assigned to IBM (326)· patent assignee history

2007–2020Based in Schoenaich, DE· patent location history

2007–2012Based in Boblingen, DE· patent location history

2008–2012Based in Boeblingen, DE· patent location history

2011–2021Based in Poughkeepsie, NY, US· patent location history

2012–2020Patents assigned to JACOBI CHRISTIAN (47)· patent assignee history

2013–2020Patents assigned to SLEGEL TIMOTHY J (27)· patent assignee history

2013–2019Patents assigned to GREINER DAN F (17)· patent assignee history

2013–2016Patents assigned to ALEXANDER KHARY J (11)· patent assignee history

2016–2021Based in West Park, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	326	2007–2021
JACOBI CHRISTIANself	47	2012–2020
SLEGEL TIMOTHY J	27	2013–2020
GREINER DAN F	17	2013–2019
ALEXANDER KHARY J	11	2013–2016

Locations

Location	Patents	Span
Poughkeepsie, New York, US	162	2011–2021
West Park, New York, US	91	2016–2021
Schoenaich, DE	53	2007–2020
Boblingen, DE	9	2007–2012
Boeblingen, DE	7	2008–2012