Inventor
RICHARD E. SCHENKER
Inventor
US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices29%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1029%
H10DInorganic electric semiconductor devices16%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
B82YSpecific uses or applications of nanostructures4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
C08FMacromolecular compounds obtained by reactions only involving carbon-to-carbon unsaturated bonds1%
C08LCompositions of macromolecular compounds1%
H10BElectronic memory devices1%
PatentTitleYear
12,293,913Directed self-assembly enabled subtractive metal patterning202512,237,223Contact over active gate structures using directed self-assembly for advanced integrated circuit structure fabrication202512,218,052Advanced lithography and self-assembled devices202512,154,855Self-aligned patterning with colored blocking and structures resulting therefrom202412,087,594Colored gratings in microelectronic structures202412,087,836Contact over active gate structures with metal oxide-caped contacts to inhibit shorting202412,080,639Contact over active gate structures with metal oxide layers to inhibit shorting202412,080,605Backside contacts for semiconductor devices202412,012,473Directed self-assembly structures and techniques202411,996,411Stacked forksheet transistors202411,990,403Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication and structures resulting therefrom202411,972,9791D vertical edge blocking (VEB) via and plug202411,854,787Advanced lithography and self-assembled devices202311,854,882Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects202311,837,644Contact over active gate structures with metal oxide-caped contacts to inhibit shorting202311,721,5801D vertical edge blocking (VEB) via and plug202311,610,810Maskless air gap enabled by a single damascene process202311,605,623Materials and layout design options for DSA on transition regions over active die202311,437,283Backside contacts for semiconductor devices202211,373,950Advanced lithography and self-assembled devices202211,373,900Damascene plug and tab patterning with photobuckets202211,239,112Passivating silicide-based approaches for conductive via fabrication and structures resulting therefrom2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2025Patents assigned to INTEL CORP (21)· patent assignee history
2022–2025Based in US· patent location history
2023Patents assigned to TAHOE RES LTD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 21 | 2022–2025 |
| TAHOE RES LTD | 1 | 2023 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 22 | 2022–2025 |