Inventor
Rita Rooyackers
Inventor
Kessel-Lo, BE
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices34%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H01LSemiconductor devices11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
B82YSpecific uses or applications of nanostructures7%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation5%
Y02PClimate change mitigation technologies in the production or processing of goods5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
G10LSpeech analysis techniques or speech synthesis2%
H10BElectronic memory devices2%
PatentTitleYear
10,236,183Monolithic integration of semiconductor materials20199,633,891'Method for forming a transistor structure comprising a fin-shaped channel structure'20179,608,094'Heterosection tunnel field-effect transistor (TFET)'20179,257,539'Method for manufacturing transistor and associated device'20169,070,720'Tunnel field effect transistor device and method for making the device'20158,576,614'Tunnel transistor, logical gate including the transistor, static random-access memory using the logical gate and method for making such a tunnel transistor'20138,415,209'Method of manufacturing a complementary nanowire tunnel field effect transistor semiconductor device'20138,034,689'Method for fabricating a semiconductor device and the semiconductor device made thereof'20117,799,664'Method for selective epitaxial growth of source/drain areas'20107,737,008'Method for making quantum dots'20107,494,902'Method of fabricating a strained multi-gate transistor'20097,157,349'Method of manufacturing a semiconductor device with field isolation regions consisting of grooves filled with isolation material'20077,033,941'Method of producing semiconductor devices using chemical mechanical polishing'20066,855,605'Semiconductor device with selectable gate thickness and method of manufacturing such devices'20056,607,950'MIS transistors with a metal gate and high-k dielectric and method of forming'20036,255,227'Etching process of CoSi2 layers'20016,153,484'Etching process of CoSi.sub.2 layers'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2019Patents assigned to IMEC VZW (5)· patent assignee history
2000–2013Based in Leuven, BE· patent location history
2001–2009Patents assigned to IMEC INTER UNI MICRO ELECTR (5)· patent assignee history
2009–2019Based in Kessel-Lo, BE· patent location history
2010–2015Patents assigned to IMEC (6)· patent assignee history
2013–2015Patents assigned to UNIV LEUVEN KATH (3)· patent assignee history
2013Patents assigned to LEONELLI DANIELE (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IMEC | 6 | 2010–2015 |
| IMEC INTER UNI MICRO ELECTR | 5 | 2001–2009 |
| IMEC VZW | 5 | 2000–2019 |
| UNIV LEUVEN KATH | 3 | 2013–2015 |
| LEONELLI DANIELE | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kessel-Lo, BE | 10 | 2009–2019 |
| Leuven, BE | 7 | 2000–2013 |