Inventor
Terry Borer
Inventor
Toronto, CA
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing85%
G01RMeasuring electric variables15%
PatentTitleYear
9,754,065'Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices'20179,122,826'Method and apparatus for performing compilation using multiple design flows'20158,589,838'M/A for performing incremental compilation using top-down and bottom-up design approaches'20138,589,849'Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices'20138,370,776'Method and apparatus for compiling intellectual property systems design cores using an incremental compile design flow'20138,250,505'Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches'20128,037,435'Directed design space exploration'20117,669,157'Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches'20107,594,208'Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage'20097,594,204'Method and apparatus for performing layout-driven optimizations on field programmable gate arrays'20097,464,362'Method and apparatus for performing incremental compilation'20087,401,314'Method and apparatus for performing compound duplication of components on field programmable gate arrays'20087,389,489'Techniques for editing circuit design files to be compatible with a new programmable IC'20087,370,295'Directed design space exploration'20087,360,190'Method and apparatus for performing retiming on field programmable gate arrays'20087,290,240'Leveraging combinations of synthesis, placement and incremental optimizations'20077,257,800'Method and apparatus for performing logic replication in field programmable gate arrays'20077,254,801'Synthesis aware placement: a novel approach that combines knowledge of possible resynthesis'20077,197,734'Method and apparatus for designing systems using logic regions'20077,194,720'Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices'20077,181,703'Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage'20077,181,717'Method and apparatus for placement of components onto programmable logic devices'20076,779,169'Method and apparatus for placement of components onto programmable logic devices'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2017Patents assigned to ALTERA CORP (23)· patent assignee history
2004–2017Based in Toronto, CA· patent location history
2012–2013Patents assigned to BORER TERRY (4)· patent assignee history
2012–2013Patents assigned to BROWN STEPHEN D (3)· patent assignee history
2012–2013Patents assigned to QUAN GABRIEL (3)· patent assignee history
2012–2013Patents assigned to KARCHMER DAVID (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALTERA CORP | 23 | 2004–2017 |
| BORER TERRYself | 4 | 2012–2013 |
| BROWN STEPHEN D | 3 | 2012–2013 |
| QUAN GABRIEL | 3 | 2012–2013 |
| KARCHMER DAVID | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Toronto, CA | 23 | 2004–2017 |