Inventor
Michelle L. Steen
Inventor
Danbury, CT, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices45%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
C23FNon-mechanical removal of metallic material from surface7%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices7%
B01DSeparation3%
G11CStatic stores3%
H10BElectronic memory devices3%
H10NElectric solid-state devices not otherwise provided for3%
PatentTitleYear
8,383,483'High performance CMOS circuits, and methods for fabricating same'20138,178,433'Methods for the formation of fully silicided metal gates'20128,080,876'Structure and method for creating reliable deep via connections in a silicon carrier'20118,035,173'CMOS transistors with differential oxygen content high-K dielectrics'20117,919,379'Dielectric spacer removal'20117,872,317'Dual metal gate self-aligned integration'20117,833,849'Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode'20107,785,999'Formation of fully silicided metal gate using dual self-aligned silicide process'20107,705,405'Methods for the formation of fully silicided metal gates'20107,696,036'CMOS transistors with differential oxygen content high-k dielectrics'20107,569,466'Dual metal gate self-aligned integration'20097,485,891'Multi-bit phase change memory cell and multi-bit phase change memory including the same, method of forming a multi-bit phase change memory, and method of programming a multi-bit phase change memory'20097,473,975'Fully silicided metal gate semiconductor device structure'20097,282,148'Porous silicon composite structure as large filtration array'20077,276,787'Silicon chip carrier with conductive through-vias and method for fabricating same'20077,273,777'Formation of fully silicided (FUSI) gate using a dual silicide process'20077,271,455'Formation of fully silicided metal gate using dual self-aligned silicide process'20077,060,624'Deep filled vias'20067,014,959'CD uniformity of chrome etch to photomask process'20067,014,958'Method for dry etching photomask material'20066,815,813'Self-contained heat sink and a method for fabricating same'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2013Patents assigned to IBM (21)· patent assignee history
2004–2013Based in Danbury, CT, US· patent location history
2011–2013Patents assigned to STEEN MICHELLE L (3)· patent assignee history
2011Patents assigned to ANDRY PAUL S (1)· patent assignee history
2012–2013Patents assigned to BIERY GLENN A (2)· patent assignee history
2013Patents assigned to ARNOLD JOHN C (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 21 | 2004–2013 |
| STEEN MICHELLE Lself | 3 | 2011–2013 |
| BIERY GLENN A | 2 | 2012–2013 |
| ANDRY PAUL S | 1 | 2011 |
| ARNOLD JOHN C | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Danbury, CT, US | 21 | 2004–2013 |