Inventor
Jason Eugene Stephens
Inventor
Menands, NY, US
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices27%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1027%
H10DInorganic electric semiconductor devices18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
G06FElectric digital data processing7%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H10BElectronic memory devices2%
H01GCapacitors1%
PatentTitleYear
10,741,439Merge mandrel features202010,559,503Methods, apparatus and system for a passthrough-based architecture202010,522,403Middle of the line self-aligned direct pattern contacts201910,340,180Merge mandrel features201910,262,941Devices and methods for forming cross coupled contacts201910,236,350Method, apparatus and system for a high density middle of line flow201910,181,420Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias201910,056,373Transistor contacts self-aligned in two dimensions20189,852,986Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit20179,825,031'Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices'20179,818,641'Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines'20179,818,623'Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit'20179,818,651'Methods, apparatus and system for a passthrough-based architecture'20179,818,640'Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines'20179,812,396'Interconnect structure for semiconductor devices with multiple power rails and redundancy'20179,786,545'Method of forming ANA regions in an integrated circuit'20179,779,943'Compensating for lithographic limitations in fabricating semiconductor interconnect structures'20179,691,626'Method of forming a pattern for interconnection lines in an integrated circuit wherein the pattern includes gamma and beta block mask portions'20179,660,040'Transistor contacts self-aligned two dimensions'20179,576,735'Vertical capacitors with spaced conductive lines'20179,530,689'Methods for fabricating integrated circuits using multi-patterning processes'20169,502,528'Borderless contact formation through metal-recess dual cap integration'20169,472,455'Methods of cross-coupling line segments on a wafer'20169,465,907'Multi-polygon constraint decomposition techniques for use in double patterning applications'20169,461,128'Method for creating self-aligned transistor contacts'20169,436,081'Methods of modifying masking reticles to remove forbidden pitch regions thereof'20169,412,655'Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines'20169,236,437'Method for creating self-aligned transistor contacts'20169,224,617'Forming cross-coupled line segments'20159,202,751'Transistor contacts self-aligned in two dimensions'20159,142,513'Middle-of-the-line constructs using diffusion contact structures'20159,006,100'Middle-of-the-line constructs using diffusion contact structures'20158,987,816'Contact power rail'20158,969,199'Methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning process'20158,946,914'Contact power rail'20158,856,715'Capacitor designs for integrated circuits utilizing self-aligned double patterning (SADP)'20148,839,168'Self-aligned double patterning via enclosure design'20148,793,627'Via non-standard limiting parameters'20148,598,633'Semiconductor device having contact layer providing electrical connections'2013Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2013–2020Patents assigned to GLOBALFOUNDRIES INC (39)· patent assignee history
2013–2015Patents assigned to AUGUR ROD (2)· patent assignee history
2013–2015Patents assigned to DENG YUNFEI (2)· patent assignee history
2013–2015Patents assigned to KENGERI SUBRAMANI (2)· patent assignee history
2013–2015Patents assigned to KYE JONGWOOK (2)· patent assignee history
2013–2015Based in Beacon, NY, US· patent location history
2014–2016Based in Cohoes, NY, US· patent location history
2015–2020Based in Menands, NY, US· patent location history
2016–2017Based in Albany, NY, US· patent location history
2017–2019Based in Hopewell Junction, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 39 | 2013–2020 |
| AUGUR ROD | 2 | 2013–2015 |
| DENG YUNFEI | 2 | 2013–2015 |
| KENGERI SUBRAMANI | 2 | 2013–2015 |
| KYE JONGWOOK | 2 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Menands, New York, US | 17 | 2015–2020 |
| Albany, New York, US | 7 | 2016–2017 |
| Cohoes, New York, US | 7 | 2014–2016 |
| Beacon, New York, US | 5 | 2013–2015 |
| Hopewell Junction, New York, US | 3 | 2017–2019 |