Inventor

John Stephen Muhich

Inventor

Austin, TX, US

Overview

50→

Patents

1987–2002

Patent span

Physics

Primary field (CPC G)

Patents· 50 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing65%

G11CStatic stores11%

H03KPulse technique6%

G09GArrangements or circuits for control of indicating devices using static means to present variable information5%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses5%

H04LTransmission of digital information, e.g. telegraphic communication3%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%

G06TImage data processing or generation, in general2%

PatentTitleYear

6,412,051'System and method for controlling a memory array in an information handling system'2002 6,389,585'Method and system for building a multiprocessor data processing system'2002 6,266,767'Apparatus and method for facilitating out-of-order execution of load instructions'2001 6,167,500'Mechanism for queuing store data and method therefor'2000 6,098,167'Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution'2000 6,079,002'Dynamic expansion of execution pipeline stages'2000 6,070,238'Method and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instruction'2000 6,055,557'Adder circuit and method therefor'2000 6,021,467'Apparatus and method for processing multiple cache misses to a single cache line'2000 6,021,512'Data processing system having memory sub-array redundancy and method therefor'2000 6,021,485'Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching'2000 6,014,047'Method and apparatus for phase rotation in a phase locked loop'2000 6,002,285'Circuitry and method for latching information'1999 5,949,262'Method and apparatus for coupled phase locked loops'1999 5,931,957'Support for out-of-order execution of loads and stores in a processor'1999 5,918,044'Apparatus and method for instruction fetching using a multi-port instruction cache directory'1999 5,913,048'Dispatching instructions in a processor supporting out-of-order execution'1999 5,887,161'Issuing instructions in a processor supporting out-of-order execution'1999 5,872,950'Method and apparatus for managing register renaming including a wraparound array and an indication of rename entry ages'1999 5,870,592'Clock generation apparatus and method for CMOS microprocessors using a differential saw oscillator'1999 5,870,582'Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched'1999 5,870,612'Method and apparatus for condensed history buffer'1999 5,864,341'Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding'1999 5,860,014'Method and apparatus for improved recovery of processor state using history buffer'1999 5,848,283'Method and system for efficient maintenance of data coherency in a multiprocessor system utilizing cache synchronization'1998 5,822,752'Method and apparatus for fast parallel determination of queue entries'1998 5,812,418'Cache sub-array method and apparatus for use in microprocessor integrated circuits'1998 5,802,571'Apparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memory'1998 5,796,998'Apparatus and method for performing branch target address calculation and branch prediciton in parallel in an information handling system'1998 5,784,604'Method and system for reduced run-time delay during conditional branch execution in pipelined processor systems utilizing selectively delayed sequential instruction purging'1998 5,758,120'Method and system for increased system memory concurrency in a multi-processor computer system utilizing concurrent access of reference and change bits'1998 5,742,784'System for reordering of instructions before placement into cache to reduce dispatch latency'1998 5,729,501'High Speed SRAM with or-gate sense'1998 5,706,464'Method and system for achieving atomic memory references in a multilevel cache data processing system'1998 5,689,198'Circuitry and method for gating information'1997 5,668,761'Fast read domino SRAM'1997 5,668,525'Comparator circuit using two bit to four bit encoder'1997 5,640,518'Addition of pre-last transfer acknowledge signal to bus interface to eliminate data bus turnaround on consecutive read and write tenures and to allow burst transfers of unknown length'1997 5,623,450'Conditional recharge for dynamic logic'1997 5,615,160'Minimal recharge overhead circuit for domino SRAM structures'1997 5,611,058'System and method for transferring information between multiple buses'1997 5,532,947'Combined decoder/adder circuit which provides improved access speed to a cache'1996 5,500,950'Data processor with speculative data transfer and address-free retry'1996 5,463,739'Apparatus for vetoing reallocation requests during a data transfer based on data bus latency and the number of received reallocation requests below a threshold'1995 5,442,766'Method and system for distributed instruction address translation in a multiscalar data processing system'1995 5,437,017'Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system'1995 4,763,251'Merge and copy bit block transfer implementation'1988 4,742,350'Software managed video synchronization generation'1988 4,740,927'Bit addressable multidimensional array'1988 4,706,074'Cursor circuit for a dual port memory'1987

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1987–2002Patents assigned to IBM (48)· patent assignee history

1987–2002Based in Austin, TX, US· patent location history

1996–2000Patents assigned to MOTOROLA INC (2)· patent assignee history

1997Based in Travis, TX, US· patent location history

1998Patents assigned to INTERNATIIONAL BUSINESS MACHIN (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	48	1987–2002
MOTOROLA INC	2	1996–2000
INTERNATIIONAL BUSINESS MACHIN	1	1998

Locations

Location	Patents	Span
Austin, Texas, US	49	1987–2002
Travis, Texas, US	1	1997