LexDanaLexDanabeta
Inventor

Michael G. Lavelle

Inventor
Saratoga, CA, US

Overview

71→
Patents
1987–2018
Patent span
Physics
Primary field (CPC G)

Patents· 71 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Tprimary
G06TImage data processing or generation, in general36%
G09GArrangements or circuits for control of indicating devices using static means to present variable information35%
G06FElectric digital data processing21%
H04NPictorial communication, e.g. television5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
G11BInformation storage based on relative movement between record carrier and transducer1%
H04LTransmission of digital information, e.g. telegraphic communication1%
PatentTitleYear
10,019,777Scalable high performance 3D graphics20189,478,001'Scalable high performance 3D graphics'20169,210,474'On screen displays associated with remote video source devices'20158,599,315'On screen displays associated with remote video source devices'20138,593,468'Scalable high performance 3D graphics'20138,311,126'Method and system for transmitting or receiving N-bit video data over a serial link'20127,808,505'Scalable high performance 3D graphics'20107,599,439'Method and system for transmitting N-bit video data over a serial link'20097,502,470'Method and apparatus for content protection within an open architecture system'20097,379,067'Scalable high performance 3D graphics'20087,145,570'Magnified texture-mapped pixel performance in a single-pixel pipeline'20067,129,941'Sample replication mode with depth value calculation'20067,106,326'System and method for computing filtered shadow estimates using reduced bandwidth'20067,027,064'Active block write-back from SRAM cache to DRAM'20067,023,444'Multi-texturing by walking an appropriately-sized supertile over a primitive'20066,999,087'Dynamically adjusting sample density in a graphics system'20066,982,719'Switching sample buffer context in response to sample requests for real-time sample filtering and video generation'20066,975,322'Dynamically adjusting a number of rendering passes in a graphics system'20056,975,317'Method for reduction of possible renderable graphics primitive shapes for rasterization'20056,963,342'Arbitration scheme for efficient parallel processing'20056,943,791'Z-slope test to optimize sample throughput'20056,924,820'Over-evaluating samples during rasterization for improved datapath utilization'20056,914,610'Graphics primitive size estimation and subdivision for use with a texture accumulation buffer'20056,906,720'Multipurpose memory system for use in a graphics system'20056,900,803'Method for rasterizing graphics for optimal tiling performance'20056,867,778'End point value correction when traversing an edge using a quantized slope value'20056,864,892'Graphics data synchronization with multiple data paths in a graphics accelerator'20056,864,900'Panning while displaying a portion of the frame buffer image'20056,859,209'Graphics data accumulation for improved multi-layer texture performance'20056,847,372'Magnified texture-mapped pixel performance in a single-pixel pipeline'20056,847,378'System and method for performing scale and bias operations by preclamping input image data'20056,847,369'Optimized packing of loose data in a graphics queue'20056,836,272'Frame buffer addressing scheme'20046,833,834'Frame buffer organization and reordering'20046,831,645'System and method for performing font operations when background color is transparent'20046,819,320'Reading or writing a non-super sampled image into a super sampled buffer'20046,816,161'Vertex assembly buffer and primitive launch buffer'20046,812,929'System and method for prefetching data from a frame buffer'20046,812,928'Performance texture mapping by combining requests for image data'20046,806,883'System and method for handling display device requests for display data from a frame buffer'20046,803,916'Rasterization using two-dimensional tiles and alternating bins for improved rendering utilization'20046,795,078'Parallel read with source-clear operation'20046,795,081'Sample cache for supersample filtering'20046,795,080'Batch processing of primitives for use with a texture accumulation buffer'20046,784,894'Mapping time-sorted to direction-sorted triangle vertices'20046,784,881'Synchronizing multiple display channels'20046,781,585'Graphics system having a super-sampled sample buffer and having single sample per pixel support'20046,778,179'External dirty tag bits for 3D-RAM SRAM'20046,778,188'Reconfigurable hardware filter for texture mapping and image processing'20046,753,870'Graphics system configured to switch between multiple sample buffer contexts'20046,731,300'Efficient anti-aliased dot rasterization'20046,720,969'Dirty tag bits for 3D-RAM SRAM'20046,670,959'Method and apparatus for reducing inefficiencies in shared memory devices'20036,661,423'Splitting grouped writes to different memory blocks'20036,654,021'Multi-channel, demand-driven display controller'20036,650,323'Graphics system having a super-sampled sample buffer and having single sample per pixel support'20036,459,428'Programmable sample filtering for image rendering'20026,262,748'Frame buffer memory with on-chip AIU and pixel cache'20016,246,422'Efficient method for storing texture maps in multi-bank memory'20016,195,106'Graphics system with multiported pixel buffers for accelerated pixel processing'20016,141,741'Computer system with a shared address bus and pipelined write operations'20006,078,587'Mechanism for coalescing non-cacheable stores'20006,020,901'Fast frame buffer system architecture for video display system'20005,963,200'Video frame synchronization of independent timing generators for frame buffers in a master-slave configuration'19995,956,046'Scene synchronization of multiple computer displays'19995,862,150'Video frame signature capture'19995,696,534'Time multiplexing pixel frame buffer video output'19975,579,473'Interface controller for frame buffer random access memory devices'19965,544,306'Flexible dram access in a frame buffer memory and system'19964,642,794'Video update FIFO buffer'19874,642,789'Video memory controller'1987

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1987Based in San Jose, CA, US· patent location history
1996–2006Patents assigned to SUN MICROSYSTEMS INC (59)· patent assignee history
1996–2018Based in Saratoga, CA, US· patent location history
2000Based in Saratogo, CA, US· patent location history
2008–2013Patents assigned to LAVELLE MICHAEL G (5)· patent assignee history
2008–2013Patents assigned to DEERING MICHAEL F (3)· patent assignee history
2008Based in Saragota, CA, US· patent location history
2009–2013Patents assigned to SILICON IMAGE INC (4)· patent assignee history
2016–2018Patents assigned to GULA CONSULTING LLC (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SUN MICROSYSTEMS INC591996–2006
LAVELLE MICHAEL Gself52008–2013
SILICON IMAGE INC42009–2013
DEERING MICHAEL F32008–2013
GULA CONSULTING LLC22016–2018
Locations
LocationPatentsSpan
Saratoga, California, US671996–2018
San Jose, California, US21987
Saragota, California, US12008
Saratogo, California, US12000