Inventor
Chang-Hwang Hua
Inventor
Tao Yuan Shien, TW
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1023%
H01LSemiconductor devices20%
H10DInorganic electric semiconductor devices13%
H10HInorganic light-emitting semiconductor devices having potential barriers5%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light3%
C23CCoating metallic material2%
C25DProcesses for the electrolytic or electrophoretic production of coatings2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution2%
PatentTitleYear
10,720,390Ohmic metal structure for GaN device202010,410,979Structure for reducing compound semiconductor wafer distortion201910,374,129Compound semiconductors having an improved high temperature resistant backside metallization201910,158,212Structure for reducing compound semiconductor wafer distortion201810,096,583Method for fabricating a semiconductor integrated chip20189,704,829'Stacked structure of semiconductor chips having via holes and metal bumps'20179,673,186'Semiconductor integrated circuit'20179,548,276'Structure of backside copper metallization for semiconductor devices and a fabrication method thereof'20179,190,374'Structure of a semiconductor chip with substrate via holes and metal bumps and a fabrication method thereof'20159,178,007'High breakdown voltage metal-insulator-metal capacitor'20158,911,551'Electroless plating apparatus and method'20148,835,283'Fabrication method for producing semiconductor chips with enhanced die strength'20148,497,206'Method of processing backside copper layer for semiconductor chips'20138,033,011'Method for mounting a thinned semiconductor wafer on a carrier substrate'20118,003,532'Method of using an electroless plating for depositing a metal seed layer for the subsequent plated backside metal film'20115,288,660'Method for forming self-aligned t-shaped transistor electrode'19945,127,984'Rapid wafer thinning process'19924,978,639'Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips'19904,842,699'Method of selective via-hole and heat sink plating using a metal mask'19894,808,273'Method of forming completely metallized via holes in semiconductors'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989–1994Patents assigned to AVANTEK (5)· patent assignee history
1989–1994Based in Palo Alto, CA, US· patent location history
2011–2020Patents assigned to WIN SEMICONDUCTORS CORP (13)· patent assignee history
2011–2018Based in Tao Yuan Shien, TW· patent location history
2013–2017Patents assigned to WIN SEMICONDUCTOR CORP (3)· patent assignee history
2013–2014Patents assigned to CHU WEN (2)· patent assignee history
2013–2014Patents assigned to HUA CHANG-HWANG (2)· patent assignee history
2018–2020Based in Taoyuan, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| WIN SEMICONDUCTORS CORP | 13 | 2011–2020 |
| AVANTEK | 5 | 1989–1994 |
| WIN SEMICONDUCTOR CORP | 3 | 2013–2017 |
| CHU WEN | 2 | 2013–2014 |
| HUA CHANG-HWANGself | 2 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tao Yuan Shien, TW | 11 | 2011–2018 |
| Palo Alto, California, US | 5 | 1989–1994 |
| Taoyuan, TW | 4 | 2018–2020 |