Inventor
Chiayao S. Tung
Inventor
Cupertino, CA, US
Overview
Patents· 13 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G09Gprimary
G09GArrangements or circuits for control of indicating devices using static means to present variable information17%
H03KPulse technique17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
H03FAmplifiers10%
G06FElectric digital data processing7%
H01LSemiconductor devices7%
H02HEmergency protective circuit arrangements7%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems7%
H04LTransmission of digital information, e.g. telegraphic communication7%
G11CStatic stores3%
PatentTitleYear
10,741,142Current mode digitally variable resistor or programmable VCOM20209,754,550'Current mode DVR or PVCOM with integrated impedances'20179,548,723'Current mode DVR or PVCOM with integrated impedances'20179,478,978'Short circuits and power limit protection circuits'20169,166,566'Current mode DVR or PVCOM with integrated impedances'20159,054,527'Short circuits and power limit protection circuits'20159,007,098'Current mode DVR or PVCOM with integrated resistors'20158,154,346'Short circuits and power limit protection circuits'20127,167,527'System and method for multi-symbol interfacing'20077,043,657'Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle'20066,937,664'System and method for multi-symbol interfacing'20056,647,506'Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle'20036,477,592'System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2007Patents assigned to INTEGRATED MEMORY LOGIC INC (5)· patent assignee history
2002–2020Based in Cupertino, CA, US· patent location history
2012Patents assigned to IML INTERNAT LTD (1)· patent assignee history
2012Patents assigned to TUNG CHIAYAO S (1)· patent assignee history
2015–2020Patents assigned to IML INT (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IML INT | 7 | 2015–2020 |
| INTEGRATED MEMORY LOGIC INC | 5 | 2002–2007 |
| IML INTERNAT LTD | 1 | 2012 |
| TUNG CHIAYAO Sself | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 13 | 2002–2020 |