Inventor
Russell J. Houghton
Inventor
Essex Junction, VT, US
Overview
Patents· 61 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores29%
H10DInorganic electric semiconductor devices13%
H03KPulse technique12%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
G05FSystems for regulating electric or magnetic variables11%
H10BElectronic memory devices9%
G06FElectric digital data processing4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H04LTransmission of digital information, e.g. telegraphic communication3%
G01KMeasuring temperature2%
PatentTitleYear
7,981,731'Method of forming a high impedance antifuse'20117,226,816'Method of forming connection and anti-fuse in layered substrate such as SOI'20077,203,102'Semiconductor memory having tri-state driver device'20077,098,083'High impedance antifuse'20066,972,220'Structures and methods of anti-fuse formation in SOI'20056,876,250'Low-power band-gap reference and temperature sensor circuit'20056,816,403'Capacitively coupled sensing apparatus and method for cross point magnetic random access memory devices'20046,812,122'Method for forming a voltage programming element'20046,790,722'Logic SOI structure, process and application for vertical bipolar transistor'20046,753,590'High impedance antifuse'20046,693,843'Wordline on and off voltage compensation circuit based on the array device threshold voltage'20046,629,291'Integrated power solution for system on chip applications'20036,596,592'Structures and methods of anti-fuse formation in SOI'20036,580,650'DRAM word line voltage control to insure full cell writeback level'20036,577,154'Constant impedance driver for high speed interface'20036,574,763'Method and apparatus for semiconductor integrated circuit testing and burn-in'20036,570,434'Method to improve charge pump reliability, efficiency and size'20036,531,911'Low-power band-gap reference and temperature sensor circuit'20036,518,827'Sense amplifier threshold compensation'20036,507,237'Low-power DC voltage generator system'20036,498,518'Low input impedance line/bus receiver'20026,492,211'Method for novel SOI DRAM BICMOS NPN'20026,436,749'Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion'20026,429,730'Bias circuit for series connected decoupling capacitors'20026,396,121'Structures and methods of anti-fuse formation in SOI'20026,388,305'Electrically programmable antifuses and methods for forming the same'20026,384,666'Antifuse latch device with controlled current programming and variable trip point'20026,369,606'Mixed threshold voltage CMOS logic device and method of manufacture therefor'20026,346,846'Methods and apparatus for blowing and sensing antifuses'20026,347,058'Sense amplifier with overdrive and regulated bitline voltage'20026,337,595'Low-power DC voltage generator system'20026,330,697'Apparatus and method for performing a defect leakage screen test for memory devices'20016,281,731'Control of hysteresis characteristic within a CMOS differential receiver'20016,271,717'Bias circuit for series connected decoupling capacitors'20016,268,748'Module with low leakage driver circuits and method of operation'20016,243,283'Impedance control using fuses'20016,222,395'Single-ended semiconductor receiver with built in threshold voltage difference'20016,204,723'Bias circuit for series connected decoupling capacitors'20016,195,027'Capacitive precharging and discharging network for converting N bit input into M bit output'20016,177,817'Compensated-current mirror off-chip driver'20016,177,807'High frequency valid data strobe'20016,141,245'Impedance control using fuses'20006,121,106'Method for forming an integrated trench capacitor'20006,111,425'Very low power logic circuit family with enhanced noise immunity'20006,087,820'Current source'20005,998,981'Weak inversion NMOS regulator with boosted gate'19995,909,400'Three device BICMOS gain cell'19995,907,251'Low voltage swing capacitive bus driver device'19995,880,988'Reference potential for sensing data in electronic storage element'19995,761,114'Multi-level storage gain cell with stepline'19985,757,693'Gain memory cell with diode'19985,532,969'Clocking circuit with increasing delay as supply voltage VDD'19965,440,258'Off-chip driver with voltage regulated predrive'19955,255,224'Boosted drive system for master/local word line memory architecture'19935,221,864'Stable voltage reference circuit with high Vt devices'19934,719,418'Defect leakage screen system'19884,413,191'Array word line driver system'19834,338,532'Integrated delay circuits'19824,308,595'Array driver'19814,279,023'Sense latch'19814,181,981'Bipolar two device dynamic memory cell'1980Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1980–2011Patents assigned to IBM (60)· patent assignee history
1980–2011Based in Essex Junction, VT, US· patent location history
2000Patents assigned to SIEMENS AG (1)· patent assignee history
2001–2003Based in Essex, VT, US· patent location history
2003–2007Patents assigned to INFINEON TECHNOLOGIES AG (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 60 | 1980–2011 |
| INFINEON TECHNOLOGIES AG | 3 | 2003–2007 |
| SIEMENS AG | 1 | 2000 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 58 | 1980–2011 |
| Essex, VT, US | 3 | 2001–2003 |