Inventor
Chris E. Barns
Inventor
Portland, OR, US
Overview
Patents· 41 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices33%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
B24BMachines, devices, or processes for grinding or polishing5%
C25FProcesses for the electrolytic removal of materials from objects3%
B23HWorking of metal by the action of a high concentration of electric current on a workpiece using an electrode which takes the place of a tool1%
B82YSpecific uses or applications of nanostructures1%
G01BMeasuring length, thickness or similar linear dimensions1%
G01DMeasuring not specially adapted for a specific variable1%
PatentTitleYear
10,598,521Metrology system20208,148,786'Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate'20127,883,951'CMOS device with metal and silicide gate electrodes and a method for making it'20117,754,552'Preventing silicide formation at the gate electrode in a replacement metal gate technology'20107,671,471'Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode'20107,666,465'Introducing nanotubes in trenches and structures formed thereby'20107,569,443'Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate'20097,422,936'Facilitating removal of sacrificial layers via implantation to form replacement metal gates'20087,355,281'Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode'20087,316,949'Integrating n-type and p-type metal gate transistors'20087,294,931'Method and apparatus for selective deposition'20077,271,045'Etch stop and hard mask film property matching to enable improved replacement metal gate process'20077,238,610'Method and apparatus for selective deposition'20077,239,019'Selectively converted inter-layer dielectric'20077,220,635'Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer'20077,217,611'Methods for integrating replacement metal gate structures'20077,208,361'Replacement gate process for making a semiconductor device that includes a metal gate electrode'20077,205,236'Semiconductor substrate polishing methods and equipment'20077,183,184'Method for making a semiconductor device that includes a metal gate electrode'20077,166,506'Poly open polish process'20077,157,378'Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode'20077,153,784'Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode'20067,153,734'CMOS device with metal and silicide gate electrodes and a method for making it'20067,144,816'Polysilicon opening polish'20067,138,323'Planarizing a semiconductor structure to form replacement metal gates'20067,126,199'Multilayer metal gate electrode'20067,109,557'Sacrificial dielectric planarization layer'20067,078,282'Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films'20067,045,428'Method for making a semiconductor device with a high-k gate dielectric and a conductor that facilitates current flow across a P/N junction'20067,018,918'Method of forming a selectively converted inter-layer dielectric using a porogen material'20066,972,225'integrating n-type and P-type metal gate transistors'20056,953,719'Integrating n-type and p-type metal gate transistors'20056,943,121'Selectively converted inter-layer dielectric'20056,908,863'Sacrificial dielectric planarization layer'20056,858,483'Integrating n-type and p-type metal gate transistors'20056,743,683'Polysilicon opening polish'20046,705,928'Through-pad slurry delivery for chemical-mechanical polish'20046,558,562'Work piece wand and method for processing work pieces using a work piece handling wand'20036,464,855'Method and apparatus for electrochemical planarization of a workpiece'20025,851,140'Semiconductor wafer polishing apparatus with a flexible carrier plate'19984,957,357'Multiple axis reticle'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990Based in Mountain View, CA, US· patent location history
1998–2012Based in Portland, OR, US· patent location history
2002–2003Patents assigned to SPEEDFAM IPEC CORP (2)· patent assignee history
2004–2012Patents assigned to INTEL CORP (36)· patent assignee history
2012Patents assigned to BARNS CHRIS E (1)· patent assignee history
2012Patents assigned to BRASK JUSTIN K (1)· patent assignee history
2012Patents assigned to CAPPELLANI ANNALISA (1)· patent assignee history
2020Based in Wilsonville, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 36 | 2004–2012 |
| SPEEDFAM IPEC CORP | 2 | 2002–2003 |
| BARNS CHRIS Eself | 1 | 2012 |
| BRASK JUSTIN K | 1 | 2012 |
| CAPPELLANI ANNALISA | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 39 | 1998–2012 |
| Wilsonville, OR, US | 1 | 2020 |
| Mountain View, California, US | 1 | 1990 |