Inventor
Kiyoyuki Shiroshima
Inventor
Hyogo, JP
Overview
Patents· 5 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores27%
H10DInorganic electric semiconductor devices27%
H10BElectronic memory devices18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%
PatentTitleYear
6,092,227'Test circuit'20006,043,522'Field effect transistor array including doped two-cell isolation region for preventing latchup'20006,040,614'Semiconductor integrated circuit including a capacitor and a fuse element'20005,973,953'Semiconductor memory device having improved bit line structure'19995,926,429'Semiconductor memory device and method of refreshing semiconductor memory device'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2000Patents assigned to MITSUBISHI ELEC SYS LSI DESIGN (5)· patent assignee history
1999–2000Patents assigned to MITSUBISHI ELECTRIC CORP (5)· patent assignee history
1999–2000Based in Hyogo, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MITSUBISHI ELEC SYS LSI DESIGN | 5 | 1999–2000 |
| MITSUBISHI ELECTRIC CORP | 5 | 1999–2000 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hyogo, JP | 5 | 1999–2000 |